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diff --git a/devdocs/gcc~13/powerpc-function-attributes.html b/devdocs/gcc~13/powerpc-function-attributes.html new file mode 100644 index 00000000..dfead296 --- /dev/null +++ b/devdocs/gcc~13/powerpc-function-attributes.html @@ -0,0 +1,81 @@ +<div class="subsection-level-extent" id="PowerPC-Function-Attributes"> <div class="nav-panel"> <p> Next: <a href="risc-v-function-attributes" accesskey="n" rel="next">RISC-V Function Attributes</a>, Previous: <a href="nvidia-ptx-function-attributes" accesskey="p" rel="prev">Nvidia PTX Function Attributes</a>, Up: <a href="function-attributes" accesskey="u" rel="up">Declaring Attributes of Functions</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div> <h1 class="subsection" id="PowerPC-Function-Attributes-1"><span>6.33.24 PowerPC Function Attributes<a class="copiable-link" href="#PowerPC-Function-Attributes-1"> ¶</a></span></h1> <p>These function attributes are supported by the PowerPC back end: </p> <dl class="table"> <dt> + <span><code class="code">longcall</code><a class="copiable-link" href="#index-indirect-calls_002c-PowerPC"> ¶</a></span> +</dt> <dt><code class="code">shortcall</code></dt> <dd> +<p>The <code class="code">longcall</code> attribute indicates that the function might be far away from the call site and require a different (more expensive) calling sequence. The <code class="code">shortcall</code> attribute indicates that the function is always close enough for the shorter calling sequence to be used. These attributes override both the <samp class="option">-mlongcall</samp> switch and the <code class="code">#pragma longcall</code> setting. </p> <p>See <a class="xref" href="rs_002f6000-and-powerpc-options">IBM RS/6000 and PowerPC Options</a>, for more information on whether long calls are necessary. </p> </dd> <dt> +<span><code class="code">target (<var class="var">options</var>)</code><a class="copiable-link" href="#index-target-function-attribute-3"> ¶</a></span> +</dt> <dd> +<p>As discussed in <a class="ref" href="common-function-attributes">Common Function Attributes</a>, this attribute allows specification of target-specific compilation options. </p> <p>On the PowerPC, the following options are allowed: </p> <dl class="table"> <dt> +<span>‘<samp class="samp">altivec</samp>’<a class="copiable-link" href="#index-target_0028_0022altivec_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-altivec</samp>’</dt> <dd> +<p>Generate code that uses (does not use) AltiVec instructions. In 32-bit code, you cannot enable AltiVec instructions unless <samp class="option">-mabi=altivec</samp> is used on the command line. </p> </dd> <dt> +<span>‘<samp class="samp">cmpb</samp>’<a class="copiable-link" href="#index-target_0028_0022cmpb_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-cmpb</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. </p> </dd> <dt> +<span>‘<samp class="samp">dlmzb</samp>’<a class="copiable-link" href="#index-target_0028_0022dlmzb_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-dlmzb</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the string-search ‘<samp class="samp">dlmzb</samp>’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors. </p> </dd> <dt> +<span>‘<samp class="samp">fprnd</samp>’<a class="copiable-link" href="#index-target_0028_0022fprnd_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-fprnd</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. </p> </dd> <dt> +<span>‘<samp class="samp">hard-dfp</samp>’<a class="copiable-link" href="#index-target_0028_0022hard-dfp_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-hard-dfp</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the decimal floating-point instructions implemented on some POWER processors. </p> </dd> <dt> +<span>‘<samp class="samp">isel</samp>’<a class="copiable-link" href="#index-target_0028_0022isel_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-isel</samp>’</dt> <dd> +<p>Generate code that uses (does not use) ISEL instruction. </p> </dd> <dt> +<span>‘<samp class="samp">mfcrf</samp>’<a class="copiable-link" href="#index-target_0028_0022mfcrf_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-mfcrf</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. </p> </dd> <dt> +<span>‘<samp class="samp">mulhw</samp>’<a class="copiable-link" href="#index-target_0028_0022mulhw_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-mulhw</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors. </p> </dd> <dt> +<span>‘<samp class="samp">multiple</samp>’<a class="copiable-link" href="#index-target_0028_0022multiple_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-multiple</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. </p> </dd> <dt> +<span>‘<samp class="samp">update</samp>’<a class="copiable-link" href="#index-target_0028_0022update_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-update</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. </p> </dd> <dt> +<span>‘<samp class="samp">popcntb</samp>’<a class="copiable-link" href="#index-target_0028_0022popcntb_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-popcntb</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. </p> </dd> <dt> +<span>‘<samp class="samp">popcntd</samp>’<a class="copiable-link" href="#index-target_0028_0022popcntd_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-popcntd</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture. </p> </dd> <dt> +<span>‘<samp class="samp">powerpc-gfxopt</samp>’<a class="copiable-link" href="#index-target_0028_0022powerpc-gfxopt_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-powerpc-gfxopt</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the optional PowerPC architecture instructions in the Graphics group, including floating-point select. </p> </dd> <dt> +<span>‘<samp class="samp">powerpc-gpopt</samp>’<a class="copiable-link" href="#index-target_0028_0022powerpc-gpopt_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-powerpc-gpopt</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. </p> </dd> <dt> +<span>‘<samp class="samp">recip-precision</samp>’<a class="copiable-link" href="#index-target_0028_0022recip-precision_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-recip-precision</samp>’</dt> <dd> +<p>Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI. </p> </dd> <dt> +<span>‘<samp class="samp">string</samp>’<a class="copiable-link" href="#index-target_0028_0022string_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-string</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. </p> </dd> <dt> +<span>‘<samp class="samp">vsx</samp>’<a class="copiable-link" href="#index-target_0028_0022vsx_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-vsx</samp>’</dt> <dd> +<p>Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. In 32-bit code, you cannot enable VSX or AltiVec instructions unless <samp class="option">-mabi=altivec</samp> is used on the command line. </p> </dd> <dt> +<span>‘<samp class="samp">friz</samp>’<a class="copiable-link" href="#index-target_0028_0022friz_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-friz</samp>’</dt> <dd> +<p>Generate (do not generate) the <code class="code">friz</code> instruction when the <samp class="option">-funsafe-math-optimizations</samp> option is used to optimize rounding a floating-point value to 64-bit integer and back to floating point. The <code class="code">friz</code> instruction does not return the same value if the floating-point number is too large to fit in an integer. </p> </dd> <dt> +<span>‘<samp class="samp">avoid-indexed-addresses</samp>’<a class="copiable-link" href="#index-target_0028_0022avoid-indexed-addresses_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-avoid-indexed-addresses</samp>’</dt> <dd> +<p>Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. </p> </dd> <dt> +<span>‘<samp class="samp">paired</samp>’<a class="copiable-link" href="#index-target_0028_0022paired_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-paired</samp>’</dt> <dd> +<p>Generate code that uses (does not use) the generation of PAIRED simd instructions. </p> </dd> <dt> +<span>‘<samp class="samp">longcall</samp>’<a class="copiable-link" href="#index-target_0028_0022longcall_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dt>‘<samp class="samp">no-longcall</samp>’</dt> <dd> +<p>Generate code that assumes (does not assume) that all calls are far away so that a longer more expensive calling sequence is required. </p> </dd> <dt> +<span>‘<samp class="samp">cpu=<var class="var">CPU</var></samp>’<a class="copiable-link" href="#index-target_0028_0022cpu_003dCPU_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dd> +<p>Specify the architecture to generate code for when compiling the function. If you select the <code class="code">target("cpu=power7")</code> attribute when generating 32-bit code, VSX and AltiVec instructions are not generated unless you use the <samp class="option">-mabi=altivec</samp> option on the command line. </p> </dd> <dt> +<span>‘<samp class="samp">tune=<var class="var">TUNE</var></samp>’<a class="copiable-link" href="#index-target_0028_0022tune_003dTUNE_0022_0029-function-attribute_002c-PowerPC"> ¶</a></span> +</dt> <dd><p>Specify the architecture to tune for when compiling the function. If you do not specify the <code class="code">target("tune=<var class="var">TUNE</var>")</code> attribute and you do specify the <code class="code">target("cpu=<var class="var">CPU</var>")</code> attribute, compilation tunes for the <var class="var">CPU</var> architecture, and not the default tuning specified on the command line. </p></dd> </dl> <p>On the PowerPC, the inliner does not inline a function that has different target options than the caller, unless the callee has a subset of the target options of the caller. </p> +</dd> </dl> </div> <div class="nav-panel"> <p> Next: <a href="risc-v-function-attributes">RISC-V Function Attributes</a>, Previous: <a href="nvidia-ptx-function-attributes">Nvidia PTX Function Attributes</a>, Up: <a href="function-attributes">Declaring Attributes of Functions</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution"> + <p class="_attribution-p"> + © Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br> + <a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/PowerPC-Function-Attributes.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/PowerPC-Function-Attributes.html</a> + </p> +</div> |