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diff --git a/devdocs/gcc~13/risc-v-options.html b/devdocs/gcc~13/risc-v-options.html new file mode 100644 index 00000000..33089f3b --- /dev/null +++ b/devdocs/gcc~13/risc-v-options.html @@ -0,0 +1,78 @@ +<div class="subsection-level-extent" id="RISC-V-Options"> <div class="nav-panel"> <p> Next: <a href="rl78-options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="pru-options" accesskey="p" rel="prev">PRU Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div> <h1 class="subsection" id="RISC-V-Options-1"><span>3.19.40 RISC-V Options<a class="copiable-link" href="#RISC-V-Options-1"> ¶</a></span></h1> <p>These command-line options are defined for RISC-V targets: </p> <dl class="table"> <dt> +<span><code class="code">-mbranch-cost=<var class="var">n</var></code><a class="copiable-link" href="#index-mbranch-cost-4"> ¶</a></span> +</dt> <dd> +<p>Set the cost of branches to roughly <var class="var">n</var> instructions. </p> </dd> <dt> +<span><code class="code">-mplt</code><a class="copiable-link" href="#index-plt"> ¶</a></span> +</dt> <dt><code class="code">-mno-plt</code></dt> <dd> +<p>When generating PIC code, do or don’t allow the use of PLTs. Ignored for non-PIC. The default is <samp class="option">-mplt</samp>. </p> </dd> <dt> +<span><code class="code">-mabi=<var class="var">ABI-string</var></code><a class="copiable-link" href="#index-mabi-4"> ¶</a></span> +</dt> <dd> +<p>Specify integer and floating-point calling convention. <var class="var">ABI-string</var> contains two parts: the size of integer types and the registers used for floating-point types. For example ‘<samp class="samp">-march=rv64ifd -mabi=lp64d</samp>’ means that ‘<samp class="samp">long</samp>’ and pointers are 64-bit (implicitly defining ‘<samp class="samp">int</samp>’ to be 32-bit), and that floating-point values up to 64 bits wide are passed in F registers. Contrast this with ‘<samp class="samp">-march=rv64ifd -mabi=lp64f</samp>’, which still allows the compiler to generate code that uses the F and D extensions but only allows floating-point values up to 32 bits long to be passed in registers; or ‘<samp class="samp">-march=rv64ifd -mabi=lp64</samp>’, in which no floating-point arguments will be passed in registers. </p> <p>The default for this argument is system dependent, users who want a specific calling convention should specify one explicitly. The valid calling conventions are: ‘<samp class="samp">ilp32</samp>’, ‘<samp class="samp">ilp32f</samp>’, ‘<samp class="samp">ilp32d</samp>’, ‘<samp class="samp">lp64</samp>’, ‘<samp class="samp">lp64f</samp>’, and ‘<samp class="samp">lp64d</samp>’. Some calling conventions are impossible to implement on some ISAs: for example, ‘<samp class="samp">-march=rv32if -mabi=ilp32d</samp>’ is invalid because the ABI requires 64-bit values be passed in F registers, but F registers are only 32 bits wide. There is also the ‘<samp class="samp">ilp32e</samp>’ ABI that can only be used with the ‘<samp class="samp">rv32e</samp>’ architecture. This ABI is not well specified at present, and is subject to change. </p> </dd> <dt> +<span><code class="code">-mfdiv</code><a class="copiable-link" href="#index-mfdiv"> ¶</a></span> +</dt> <dt><code class="code">-mno-fdiv</code></dt> <dd> +<p>Do or don’t use hardware floating-point divide and square root instructions. This requires the F or D extensions for floating-point registers. The default is to use them if the specified architecture has these instructions. </p> </dd> <dt> +<span><code class="code">-mdiv</code><a class="copiable-link" href="#index-mdiv-3"> ¶</a></span> +</dt> <dt><code class="code">-mno-div</code></dt> <dd> +<p>Do or don’t use hardware instructions for integer division. This requires the M extension. The default is to use them if the specified architecture has these instructions. </p> </dd> <dt> +<span><code class="code">-misa-spec=<var class="var">ISA-spec-string</var></code><a class="copiable-link" href="#index-misa-spec"> ¶</a></span> +</dt> <dd> +<p>Specify the version of the RISC-V Unprivileged (formerly User-Level) ISA specification to produce code conforming to. The possibilities for <var class="var">ISA-spec-string</var> are: </p> +<dl class="table"> <dt><code class="code">2.2</code></dt> <dd><p>Produce code conforming to version 2.2. </p></dd> <dt><code class="code">20190608</code></dt> <dd><p>Produce code conforming to version 20190608. </p></dd> <dt><code class="code">20191213</code></dt> <dd><p>Produce code conforming to version 20191213. </p></dd> </dl> <p>The default is <samp class="option">-misa-spec=20191213</samp> unless GCC has been configured with <samp class="option">--with-isa-spec=</samp> specifying a different default version. </p> </dd> <dt> +<span><code class="code">-march=<var class="var">ISA-string</var></code><a class="copiable-link" href="#index-march-14"> ¶</a></span> +</dt> <dd> +<p>Generate code for given RISC-V ISA (e.g. ‘<samp class="samp">rv64im</samp>’). ISA strings must be lower-case. Examples include ‘<samp class="samp">rv64i</samp>’, ‘<samp class="samp">rv32g</samp>’, ‘<samp class="samp">rv32e</samp>’, and ‘<samp class="samp">rv32imaf</samp>’. </p> <p>When <samp class="option">-march=</samp> is not specified, use the setting from <samp class="option">-mcpu</samp>. </p> <p>If both <samp class="option">-march</samp> and <samp class="option">-mcpu=</samp> are not specified, the default for this argument is system dependent, users who want a specific architecture extensions should specify one explicitly. </p> </dd> <dt> +<span><code class="code">-mcpu=<var class="var">processor-string</var></code><a class="copiable-link" href="#index-mcpu-8"> ¶</a></span> +</dt> <dd> +<p>Use architecture of and optimize the output for the given processor, specified by particular CPU name. Permissible values for this option are: ‘<samp class="samp">sifive-e20</samp>’, ‘<samp class="samp">sifive-e21</samp>’, ‘<samp class="samp">sifive-e24</samp>’, ‘<samp class="samp">sifive-e31</samp>’, ‘<samp class="samp">sifive-e34</samp>’, ‘<samp class="samp">sifive-e76</samp>’, ‘<samp class="samp">sifive-s21</samp>’, ‘<samp class="samp">sifive-s51</samp>’, ‘<samp class="samp">sifive-s54</samp>’, ‘<samp class="samp">sifive-s76</samp>’, ‘<samp class="samp">sifive-u54</samp>’, and ‘<samp class="samp">sifive-u74</samp>’. </p> </dd> <dt> +<span><code class="code">-mtune=<var class="var">processor-string</var></code><a class="copiable-link" href="#index-mtune-12"> ¶</a></span> +</dt> <dd> +<p>Optimize the output for the given processor, specified by microarchitecture or particular CPU name. Permissible values for this option are: ‘<samp class="samp">rocket</samp>’, ‘<samp class="samp">sifive-3-series</samp>’, ‘<samp class="samp">sifive-5-series</samp>’, ‘<samp class="samp">sifive-7-series</samp>’, ‘<samp class="samp">thead-c906</samp>’, ‘<samp class="samp">size</samp>’, and all valid options for <samp class="option">-mcpu=</samp>. </p> <p>When <samp class="option">-mtune=</samp> is not specified, use the setting from <samp class="option">-mcpu</samp>, the default is ‘<samp class="samp">rocket</samp>’ if both are not specified. </p> <p>The ‘<samp class="samp">size</samp>’ choice is not intended for use by end-users. This is used when <samp class="option">-Os</samp> is specified. It overrides the instruction cost info provided by <samp class="option">-mtune=</samp>, but does not override the pipeline info. This helps reduce code size while still giving good performance. </p> </dd> <dt> +<span><code class="code">-mpreferred-stack-boundary=<var class="var">num</var></code><a class="copiable-link" href="#index-mpreferred-stack-boundary"> ¶</a></span> +</dt> <dd> +<p>Attempt to keep the stack boundary aligned to a 2 raised to <var class="var">num</var> byte boundary. If <samp class="option">-mpreferred-stack-boundary</samp> is not specified, the default is 4 (16 bytes or 128-bits). </p> <p><strong class="strong">Warning:</strong> If you use this switch, then you must build all modules with the same value, including any libraries. This includes the system libraries and startup modules. </p> </dd> <dt> +<span><code class="code">-msmall-data-limit=<var class="var">n</var></code><a class="copiable-link" href="#index-msmall-data-limit-1"> ¶</a></span> +</dt> <dd> +<p>Put global and static data smaller than <var class="var">n</var> bytes into a special section (on some targets). </p> </dd> <dt> +<span><code class="code">-msave-restore</code><a class="copiable-link" href="#index-msave-restore"> ¶</a></span> +</dt> <dt><code class="code">-mno-save-restore</code></dt> <dd> +<p>Do or don’t use smaller but slower prologue and epilogue code that uses library function calls. The default is to use fast inline prologues and epilogues. </p> </dd> <dt> +<span><code class="code">-mshorten-memrefs</code><a class="copiable-link" href="#index-mshorten-memrefs"> ¶</a></span> +</dt> <dt><code class="code">-mno-shorten-memrefs</code></dt> <dd> +<p>Do or do not attempt to make more use of compressed load/store instructions by replacing a load/store of ’base register + large offset’ with a new load/store of ’new base + small offset’. If the new base gets stored in a compressed register, then the new load/store can be compressed. Currently targets 32-bit integer load/stores only. </p> </dd> <dt> +<span><code class="code">-mstrict-align</code><a class="copiable-link" href="#index-mstrict-align-3"> ¶</a></span> +</dt> <dt><code class="code">-mno-strict-align</code></dt> <dd> +<p>Do not or do generate unaligned memory accesses. The default is set depending on whether the processor we are optimizing for supports fast unaligned access or not. </p> </dd> <dt> +<span><code class="code">-mcmodel=medlow</code><a class="copiable-link" href="#index-mcmodel_003dmedlow"> ¶</a></span> +</dt> <dd> +<p>Generate code for the medium-low code model. The program and its statically defined symbols must lie within a single 2 GiB address range and must lie between absolute addresses −2 GiB and +2 GiB. Programs can be statically or dynamically linked. This is the default code model. </p> </dd> <dt> +<span><code class="code">-mcmodel=medany</code><a class="copiable-link" href="#index-mcmodel_003dmedany"> ¶</a></span> +</dt> <dd> +<p>Generate code for the medium-any code model. The program and its statically defined symbols must be within any single 2 GiB address range. Programs can be statically or dynamically linked. </p> <p>The code generated by the medium-any code model is position-independent, but is not guaranteed to function correctly when linked into position-independent executables or libraries. </p> </dd> <dt><code class="code">-mexplicit-relocs</code></dt> <dt><code class="code">-mno-exlicit-relocs</code></dt> <dd> +<p>Use or do not use assembler relocation operators when dealing with symbolic addresses. The alternative is to use assembler macros instead, which may limit optimization. </p> </dd> <dt> +<span><code class="code">-mrelax</code><a class="copiable-link" href="#index-mrelax-5"> ¶</a></span> +</dt> <dt><code class="code">-mno-relax</code></dt> <dd> +<p>Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. The default is to take advantage of linker relaxations. </p> </dd> <dt> +<span><code class="code">-mriscv-attribute</code><a class="copiable-link" href="#index-mriscv-attribute"> ¶</a></span> +</dt> <dt><code class="code">-mno-riscv-attribute</code></dt> <dd> +<p>Emit (do not emit) RISC-V attribute to record extra information into ELF objects. This feature requires at least binutils 2.32. </p> </dd> <dt> +<span><code class="code">-mcsr-check</code><a class="copiable-link" href="#index-mcsr-check"> ¶</a></span> +</dt> <dt><code class="code">-mno-csr-check</code></dt> <dd> +<p>Enables or disables the CSR checking. </p> </dd> <dt> +<span><code class="code">-malign-data=<var class="var">type</var></code><a class="copiable-link" href="#index-malign-data"> ¶</a></span> +</dt> <dd> +<p>Control how GCC aligns variables and constants of array, structure, or union types. Supported values for <var class="var">type</var> are ‘<samp class="samp">xlen</samp>’ which uses x register width as the alignment value, and ‘<samp class="samp">natural</samp>’ which uses natural alignment. ‘<samp class="samp">xlen</samp>’ is the default. </p> </dd> <dt> +<span><code class="code">-mbig-endian</code><a class="copiable-link" href="#index-mbig-endian-10"> ¶</a></span> +</dt> <dd> +<p>Generate big-endian code. This is the default when GCC is configured for a ‘<samp class="samp">riscv64be-*-*</samp>’ or ‘<samp class="samp">riscv32be-*-*</samp>’ target. </p> </dd> <dt> +<span><code class="code">-mlittle-endian</code><a class="copiable-link" href="#index-mlittle-endian-10"> ¶</a></span> +</dt> <dd> +<p>Generate little-endian code. This is the default when GCC is configured for a ‘<samp class="samp">riscv64-*-*</samp>’ or ‘<samp class="samp">riscv32-*-*</samp>’ but not a ‘<samp class="samp">riscv64be-*-*</samp>’ or ‘<samp class="samp">riscv32be-*-*</samp>’ target. </p> </dd> <dt> + <span><code class="code">-mstack-protector-guard=<var class="var">guard</var></code><a class="copiable-link" href="#index-mstack-protector-guard-2"> ¶</a></span> +</dt> <dt><code class="code">-mstack-protector-guard-reg=<var class="var">reg</var></code></dt> <dt><code class="code">-mstack-protector-guard-offset=<var class="var">offset</var></code></dt> <dd> +<p>Generate stack protection code using canary at <var class="var">guard</var>. Supported locations are ‘<samp class="samp">global</samp>’ for a global canary or ‘<samp class="samp">tls</samp>’ for per-thread canary in the TLS block. </p> <p>With the latter choice the options <samp class="option">-mstack-protector-guard-reg=<var class="var">reg</var></samp> and <samp class="option">-mstack-protector-guard-offset=<var class="var">offset</var></samp> furthermore specify which register to use as base register for reading the canary, and from what offset from that base register. There is no default register or offset as this is entirely for use within the Linux kernel. </p> +</dd> </dl> </div> <div class="nav-panel"> <p> Next: <a href="rl78-options">RL78 Options</a>, Previous: <a href="pru-options">PRU Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution"> + <p class="_attribution-p"> + © Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br> + <a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/RISC-V-Options.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/RISC-V-Options.html</a> + </p> +</div> |