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6.60.16 MIPS Paired-Single Support

The MIPS64 architecture includes a number of instructions that operate on pairs of single-precision floating-point values. Each pair is packed into a 64-bit floating-point register, with one element being designated the “upper half” and the other being designated the “lower half”.

GCC supports paired-single operations using both the generic vector extensions (see Using Vector Instructions through Built-in Functions) and a collection of MIPS-specific built-in functions. Both kinds of support are enabled by the -mpaired-single command-line option.

The vector type associated with paired-single values is usually called v2sf. It can be defined in C as follows: 

typedef float v2sf __attribute__ ((vector_size (8)));
+

v2sf values are initialized in the same way as aggregates. For example: 

v2sf a = {1.5, 9.1};
+v2sf b;
+float e, f;
+b = (v2sf) {e, f};
+

Note: The CPU’s endianness determines which value is stored in the upper half of a register and which value is stored in the lower half. On little-endian targets, the first value is the lower one and the second value is the upper one. The opposite order applies to big-endian targets. For example, the code above sets the lower half of a to 1.5 on little-endian targets and 9.1 on big-endian targets.

+

+ © Free Software Foundation
Licensed under the GNU Free Documentation License, Version 1.3.
+ https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/MIPS-Paired-Single-Support.html +

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