path: root/devdocs/gcc~13/arm-options.html

<div class="subsection-level-extent" id="ARM-Options"> <div class="nav-panel"> <p> Next: <a href="avr-options" accesskey="n" rel="next">AVR Options</a>, Previous: <a href="arc-options" accesskey="p" rel="prev">ARC Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="ARM-Options-1"><span>3.19.5 ARM Options<a class="copiable-link" href="#ARM-Options-1"> ¶</a></span></h1>  <p>These ‘<samp class="samp">-m</samp>’ options are defined for the ARM port: </p> <dl class="table"> <dt>
<span><code class="code">-mabi=<var class="var">name</var></code><a class="copiable-link" href="#index-mabi-1"> ¶</a></span>
</dt> <dd>
<p>Generate code for the specified ABI. Permissible values are: ‘<samp class="samp">apcs-gnu</samp>’, ‘<samp class="samp">atpcs</samp>’, ‘<samp class="samp">aapcs</samp>’, ‘<samp class="samp">aapcs-linux</samp>’ and ‘<samp class="samp">iwmmxt</samp>’. </p> </dd> <dt>
<span><code class="code">-mapcs-frame</code><a class="copiable-link" href="#index-mapcs-frame"> ¶</a></span>
</dt> <dd>
<p>Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying <samp class="option">-fomit-frame-pointer</samp> with this option causes the stack frames not to be generated for leaf functions. The default is <samp class="option">-mno-apcs-frame</samp>. This option is deprecated. </p> </dd> <dt>
<span><code class="code">-mapcs</code><a class="copiable-link" href="#index-mapcs"> ¶</a></span>
</dt> <dd>
<p>This is a synonym for <samp class="option">-mapcs-frame</samp> and is deprecated. </p> </dd> <dt>
<span><code class="code">-mthumb-interwork</code><a class="copiable-link" href="#index-mthumb-interwork"> ¶</a></span>
</dt> <dd>
<p>Generate code that supports calling between the ARM and Thumb instruction sets. Without this option, on pre-v5 architectures, the two instruction sets cannot be reliably used inside one program. The default is <samp class="option">-mno-thumb-interwork</samp>, since slightly larger code is generated when <samp class="option">-mthumb-interwork</samp> is specified. In AAPCS configurations this option is meaningless. </p> </dd> <dt>
 <span><code class="code">-mno-sched-prolog</code><a class="copiable-link" href="#index-mno-sched-prolog"> ¶</a></span>
</dt> <dd>
<p>Prevent the reordering of instructions in the function prologue, or the merging of those instruction with the instructions in the function’s body. This means that all functions start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start of functions inside an executable piece of code. The default is <samp class="option">-msched-prolog</samp>. </p> </dd> <dt>
<span><code class="code">-mfloat-abi=<var class="var">name</var></code><a class="copiable-link" href="#index-mfloat-abi"> ¶</a></span>
</dt> <dd>
<p>Specifies which floating-point ABI to use. Permissible values are: ‘<samp class="samp">soft</samp>’, ‘<samp class="samp">softfp</samp>’ and ‘<samp class="samp">hard</samp>’. </p> <p>Specifying ‘<samp class="samp">soft</samp>’ causes GCC to generate output containing library calls for floating-point operations. ‘<samp class="samp">softfp</samp>’ allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. ‘<samp class="samp">hard</samp>’ allows generation of floating-point instructions and uses FPU-specific calling conventions. </p> <p>The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries. </p> </dd> <dt>
<span><code class="code">-mgeneral-regs-only</code><a class="copiable-link" href="#index-mgeneral-regs-only-1"> ¶</a></span>
</dt> <dd>
<p>Generate code which uses only the general-purpose registers. This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler. </p> </dd> <dt>
<span><code class="code">-mlittle-endian</code><a class="copiable-link" href="#index-mlittle-endian-2"> ¶</a></span>
</dt> <dd>
<p>Generate code for a processor running in little-endian mode. This is the default for all standard configurations. </p> </dd> <dt>
<span><code class="code">-mbig-endian</code><a class="copiable-link" href="#index-mbig-endian-2"> ¶</a></span>
</dt> <dd>
<p>Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor. </p> </dd> <dt>
<span><code class="code">-mbe8</code><a class="copiable-link" href="#index-mbe8"> ¶</a></span>
</dt> <dt><code class="code">-mbe32</code></dt> <dd>
<p>When linking a big-endian image select between BE8 and BE32 formats. The option has no effect for little-endian images and is ignored. The default is dependent on the selected target architecture. For ARMv6 and later architectures the default is BE8, for older architectures the default is BE32. BE32 format has been deprecated by ARM. </p> </dd> <dt>
<span><code class="code">-march=<var class="var">name</var><span class="r">[</span>+extension…<span class="r">]</span></code><a class="copiable-link" href="#index-march-2"> ¶</a></span>
</dt> <dd>
<p>This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the <samp class="option">-mcpu=</samp> option. </p> <p>Permissible names are: ‘<samp class="samp">armv4t</samp>’, ‘<samp class="samp">armv5t</samp>’, ‘<samp class="samp">armv5te</samp>’, ‘<samp class="samp">armv6</samp>’, ‘<samp class="samp">armv6j</samp>’, ‘<samp class="samp">armv6k</samp>’, ‘<samp class="samp">armv6kz</samp>’, ‘<samp class="samp">armv6t2</samp>’, ‘<samp class="samp">armv6z</samp>’, ‘<samp class="samp">armv6zk</samp>’, ‘<samp class="samp">armv7</samp>’, ‘<samp class="samp">armv7-a</samp>’, ‘<samp class="samp">armv7ve</samp>’, ‘<samp class="samp">armv8-a</samp>’, ‘<samp class="samp">armv8.1-a</samp>’, ‘<samp class="samp">armv8.2-a</samp>’, ‘<samp class="samp">armv8.3-a</samp>’, ‘<samp class="samp">armv8.4-a</samp>’, ‘<samp class="samp">armv8.5-a</samp>’, ‘<samp class="samp">armv8.6-a</samp>’, ‘<samp class="samp">armv9-a</samp>’, ‘<samp class="samp">armv7-r</samp>’, ‘<samp class="samp">armv8-r</samp>’, ‘<samp class="samp">armv6-m</samp>’, ‘<samp class="samp">armv6s-m</samp>’, ‘<samp class="samp">armv7-m</samp>’, ‘<samp class="samp">armv7e-m</samp>’, ‘<samp class="samp">armv8-m.base</samp>’, ‘<samp class="samp">armv8-m.main</samp>’, ‘<samp class="samp">armv8.1-m.main</samp>’, ‘<samp class="samp">armv9-a</samp>’, ‘<samp class="samp">iwmmxt</samp>’ and ‘<samp class="samp">iwmmxt2</samp>’. </p> <p>Additionally, the following architectures, which lack support for the Thumb execution state, are recognized but support is deprecated: ‘<samp class="samp">armv4</samp>’. </p> <p>Many of the architectures support extensions. These can be added by appending ‘<samp class="samp">+<var class="var">extension</var></samp>’ to the architecture name. Extension options are processed in order and capabilities accumulate. An extension will also enable any necessary base extensions upon which it depends. For example, the ‘<samp class="samp">+crypto</samp>’ extension will always enable the ‘<samp class="samp">+simd</samp>’ extension. The exception to the additive construction is for extensions that are prefixed with ‘<samp class="samp">+no…</samp>’: these extensions disable the specified option and any other extensions that may depend on the presence of that extension. </p> <p>For example, ‘<samp class="samp">-march=armv7-a+simd+nofp+vfpv4</samp>’ is equivalent to writing ‘<samp class="samp">-march=armv7-a+vfpv4</samp>’ since the ‘<samp class="samp">+simd</samp>’ option is entirely disabled by the ‘<samp class="samp">+nofp</samp>’ option that follows it. </p> <p>Most extension names are generically named, but have an effect that is dependent upon the architecture to which it is applied. For example, the ‘<samp class="samp">+simd</samp>’ option can be applied to both ‘<samp class="samp">armv7-a</samp>’ and ‘<samp class="samp">armv8-a</samp>’ architectures, but will enable the original ARMv7-A Advanced SIMD (Neon) extensions for ‘<samp class="samp">armv7-a</samp>’ and the ARMv8-A variant for ‘<samp class="samp">armv8-a</samp>’. </p> <p>The table below lists the supported extensions for each architecture. Architectures not mentioned do not support any extensions. </p> <dl class="table"> <dt>‘<samp class="samp">armv5te</samp>’</dt> <dt>‘<samp class="samp">armv6</samp>’</dt> <dt>‘<samp class="samp">armv6j</samp>’</dt> <dt>‘<samp class="samp">armv6k</samp>’</dt> <dt>‘<samp class="samp">armv6kz</samp>’</dt> <dt>‘<samp class="samp">armv6t2</samp>’</dt> <dt>‘<samp class="samp">armv6z</samp>’</dt> <dt>‘<samp class="samp">armv6zk</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The VFPv2 floating-point instructions. The extension ‘<samp class="samp">+vfpv2</samp>’ can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv7</samp>’</dt> <dd>
<p>The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures. </p>
<dl class="table"> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 16 double-precision registers. The extension ‘<samp class="samp">+vfpv3-d16</samp>’ can be used as an alias for this extension. Note that floating-point is not supported by the base ARMv7-M architecture, but is compatible with both the ARMv7-A and ARMv7-R architectures. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv7-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+mp</samp>’</dt> <dd>
<p>The multiprocessing extension. </p> </dd> <dt>‘<samp class="samp">+sec</samp>’</dt> <dd>
<p>The security extension. </p> </dd> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 16 double-precision registers. The extension ‘<samp class="samp">+vfpv3-d16</samp>’ can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extensions ‘<samp class="samp">+neon</samp>’ and ‘<samp class="samp">+neon-vfpv3</samp>’ can be used as aliases for this extension. </p> </dd> <dt>‘<samp class="samp">+vfpv3</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 32 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+vfpv3-d16-fp16</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+vfpv3-fp16</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+vfpv4-d16</samp>’</dt> <dd>
<p>The VFPv4 floating-point instructions, with 16 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+vfpv4</samp>’</dt> <dd>
<p>The VFPv4 floating-point instructions, with 32 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+neon-fp16</samp>’</dt> <dd>
<p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+neon-vfpv4</samp>’</dt> <dd>
<p>The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+nosimd</samp>’</dt> <dd>
<p>Disable the Advanced SIMD instructions (does not disable floating point). </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point and Advanced SIMD instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv7ve</samp>’</dt> <dd>
<p>The extended version of the ARMv7-A architecture with support for virtualization. </p>
<dl class="table"> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The VFPv4 floating-point instructions, with 16 double-precision registers. The extension ‘<samp class="samp">+vfpv4-d16</samp>’ can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The extension ‘<samp class="samp">+neon-vfpv4</samp>’ can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+vfpv3-d16</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 16 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+vfpv3</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 32 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+vfpv3-d16-fp16</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+vfpv3-fp16</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+vfpv4-d16</samp>’</dt> <dd>
<p>The VFPv4 floating-point instructions, with 16 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+vfpv4</samp>’</dt> <dd>
<p>The VFPv4 floating-point instructions, with 32 double-precision registers. </p> </dd> <dt>‘<samp class="samp">+neon</samp>’</dt> <dd>
<p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extension ‘<samp class="samp">+neon-vfpv3</samp>’ can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+neon-fp16</samp>’</dt> <dd>
<p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+nosimd</samp>’</dt> <dd>
<p>Disable the Advanced SIMD instructions (does not disable floating point). </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point and Advanced SIMD instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+crc</samp>’</dt> <dd><p>The Cyclic Redundancy Check (CRC) instructions. </p></dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd><p>The ARMv8-A Advanced SIMD and floating-point instructions. </p></dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd><p>The cryptographic instructions. </p></dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd><p>Disable the cryptographic instructions. </p></dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p></dd> <dt>‘<samp class="samp">+sb</samp>’</dt> <dd><p>Speculation Barrier Instruction. </p></dd> <dt>‘<samp class="samp">+predres</samp>’</dt> <dd><p>Execution and Data Prediction Restriction Instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8.1-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The ARMv8.1-A Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd>
<p>The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd>
<p>Disable the cryptographic instructions. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p> </dd> <dt>‘<samp class="samp">+sb</samp>’</dt> <dd>
<p>Speculation Barrier Instruction. </p> </dd> <dt>‘<samp class="samp">+predres</samp>’</dt> <dd><p>Execution and Data Prediction Restriction Instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8.2-a</samp>’</dt> <dt>‘<samp class="samp">armv8.3-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp16</samp>’</dt> <dd>
<p>The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+fp16fml</samp>’</dt> <dd>
<p>The half-precision floating-point fmla extension. This also enables the half-precision floating-point extension and Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The ARMv8.1-A Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd>
<p>The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+dotprod</samp>’</dt> <dd>
<p>Enable the Dot Product extension. This also enables Advanced SIMD instructions. </p> </dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd>
<p>Disable the cryptographic extension. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p> </dd> <dt>‘<samp class="samp">+sb</samp>’</dt> <dd>
<p>Speculation Barrier Instruction. </p> </dd> <dt>‘<samp class="samp">+predres</samp>’</dt> <dd>
<p>Execution and Data Prediction Restriction Instructions. </p> </dd> <dt>‘<samp class="samp">+i8mm</samp>’</dt> <dd>
<p>8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+bf16</samp>’</dt> <dd><p>Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8.4-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp16</samp>’</dt> <dd>
<p>The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension. </p> </dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension. </p> </dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd>
<p>The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension. </p> </dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd>
<p>Disable the cryptographic extension. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p> </dd> <dt>‘<samp class="samp">+sb</samp>’</dt> <dd>
<p>Speculation Barrier Instruction. </p> </dd> <dt>‘<samp class="samp">+predres</samp>’</dt> <dd>
<p>Execution and Data Prediction Restriction Instructions. </p> </dd> <dt>‘<samp class="samp">+i8mm</samp>’</dt> <dd>
<p>8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+bf16</samp>’</dt> <dd><p>Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8.5-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp16</samp>’</dt> <dd>
<p>The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension. </p> </dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension. </p> </dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd>
<p>The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension. </p> </dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd>
<p>Disable the cryptographic extension. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p> </dd> <dt>‘<samp class="samp">+i8mm</samp>’</dt> <dd>
<p>8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+bf16</samp>’</dt> <dd><p>Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8.6-a</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp16</samp>’</dt> <dd>
<p>The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension. </p> </dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd>
<p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension. </p> </dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd>
<p>The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension. </p> </dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd>
<p>Disable the cryptographic extension. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p> </dd> <dt>‘<samp class="samp">+i8mm</samp>’</dt> <dd>
<p>8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+bf16</samp>’</dt> <dd><p>Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv7-r</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp.sp</samp>’</dt> <dd>
<p>The single-precision VFPv3 floating-point instructions. The extension ‘<samp class="samp">+vfpv3xd</samp>’ can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions with 16 double-precision registers. The extension +vfpv3-d16 can be used as an alias for this extension. </p> </dd> <dt>‘<samp class="samp">+vfpv3xd-d16-fp16</samp>’</dt> <dd>
<p>The single-precision VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+vfpv3-d16-fp16</samp>’</dt> <dd>
<p>The VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point extension. </p> </dd> <dt>‘<samp class="samp">+idiv</samp>’</dt> <dd>
<p>The ARM-state integer division instructions. </p> </dd> <dt>‘<samp class="samp">+noidiv</samp>’</dt> <dd><p>Disable the ARM-state integer division extension. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv7e-m</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The single-precision VFPv4 floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+fpv5</samp>’</dt> <dd>
<p>The single-precision FPv5 floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+fp.dp</samp>’</dt> <dd>
<p>The single- and double-precision FPv5 floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point extensions. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8.1-m.main</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+dsp</samp>’</dt> <dd>
<p>The DSP instructions. </p> </dd> <dt>‘<samp class="samp">+mve</samp>’</dt> <dd>
<p>The M-Profile Vector Extension (MVE) integer instructions. </p> </dd> <dt>‘<samp class="samp">+mve.fp</samp>’</dt> <dd>
<p>The M-Profile Vector Extension (MVE) integer and single precision floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The single-precision floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+fp.dp</samp>’</dt> <dd>
<p>The single- and double-precision floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point extension. </p> </dd> <dt>‘<samp class="samp">+cdecp0, +cdecp1, ... , +cdecp7</samp>’</dt> <dd>
<p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7. </p> </dd> <dt>‘<samp class="samp">+pacbti</samp>’</dt> <dd><p>Enable the Pointer Authentication and Branch Target Identification Extension. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8-m.main</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+dsp</samp>’</dt> <dd>
<p>The DSP instructions. </p> </dd> <dt>‘<samp class="samp">+nodsp</samp>’</dt> <dd>
<p>Disable the DSP extension. </p> </dd> <dt>‘<samp class="samp">+fp</samp>’</dt> <dd>
<p>The single-precision floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+fp.dp</samp>’</dt> <dd>
<p>The single- and double-precision floating-point instructions. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disable the floating-point extension. </p> </dd> <dt>‘<samp class="samp">+cdecp0, +cdecp1, ... , +cdecp7</samp>’</dt> <dd><p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7. </p></dd> </dl> </dd> <dt>‘<samp class="samp">armv8-r</samp>’</dt> <dd>
<dl class="table"> <dt>‘<samp class="samp">+crc</samp>’</dt> <dd><p>The Cyclic Redundancy Check (CRC) instructions. </p></dd> <dt>‘<samp class="samp">+fp.sp</samp>’</dt> <dd><p>The single-precision FPv5 floating-point instructions. </p></dd> <dt>‘<samp class="samp">+simd</samp>’</dt> <dd><p>The ARMv8-A Advanced SIMD and floating-point instructions. </p></dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd><p>The cryptographic instructions. </p></dd> <dt>‘<samp class="samp">+nocrypto</samp>’</dt> <dd><p>Disable the cryptographic instructions. </p></dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. </p></dd> </dl> </dd> </dl> <p><samp class="option">-march=native</samp> causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. </p> </dd> <dt>
<span><code class="code">-mtune=<var class="var">name</var></code><a class="copiable-link" href="#index-mtune-4"> ¶</a></span>
</dt> <dd>
<p>This option specifies the name of the target ARM processor for which GCC should tune the performance of the code. For some ARM implementations better performance can be obtained by using this option. Permissible names are: ‘<samp class="samp">arm7tdmi</samp>’, ‘<samp class="samp">arm7tdmi-s</samp>’, ‘<samp class="samp">arm710t</samp>’, ‘<samp class="samp">arm720t</samp>’, ‘<samp class="samp">arm740t</samp>’, ‘<samp class="samp">strongarm</samp>’, ‘<samp class="samp">strongarm110</samp>’, ‘<samp class="samp">strongarm1100</samp>’, ‘<samp class="samp">strongarm1110</samp>’, ‘<samp class="samp">arm8</samp>’, ‘<samp class="samp">arm810</samp>’, ‘<samp class="samp">arm9</samp>’, ‘<samp class="samp">arm9e</samp>’, ‘<samp class="samp">arm920</samp>’, ‘<samp class="samp">arm920t</samp>’, ‘<samp class="samp">arm922t</samp>’, ‘<samp class="samp">arm946e-s</samp>’, ‘<samp class="samp">arm966e-s</samp>’, ‘<samp class="samp">arm968e-s</samp>’, ‘<samp class="samp">arm926ej-s</samp>’, ‘<samp class="samp">arm940t</samp>’, ‘<samp class="samp">arm9tdmi</samp>’, ‘<samp class="samp">arm10tdmi</samp>’, ‘<samp class="samp">arm1020t</samp>’, ‘<samp class="samp">arm1026ej-s</samp>’, ‘<samp class="samp">arm10e</samp>’, ‘<samp class="samp">arm1020e</samp>’, ‘<samp class="samp">arm1022e</samp>’, ‘<samp class="samp">arm1136j-s</samp>’, ‘<samp class="samp">arm1136jf-s</samp>’, ‘<samp class="samp">mpcore</samp>’, ‘<samp class="samp">mpcorenovfp</samp>’, ‘<samp class="samp">arm1156t2-s</samp>’, ‘<samp class="samp">arm1156t2f-s</samp>’, ‘<samp class="samp">arm1176jz-s</samp>’, ‘<samp class="samp">arm1176jzf-s</samp>’, ‘<samp class="samp">generic-armv7-a</samp>’, ‘<samp class="samp">cortex-a5</samp>’, ‘<samp class="samp">cortex-a7</samp>’, ‘<samp class="samp">cortex-a8</samp>’, ‘<samp class="samp">cortex-a9</samp>’, ‘<samp class="samp">cortex-a12</samp>’, ‘<samp class="samp">cortex-a15</samp>’, ‘<samp class="samp">cortex-a17</samp>’, ‘<samp class="samp">cortex-a32</samp>’, ‘<samp class="samp">cortex-a35</samp>’, ‘<samp class="samp">cortex-a53</samp>’, ‘<samp class="samp">cortex-a55</samp>’, ‘<samp class="samp">cortex-a57</samp>’, ‘<samp class="samp">cortex-a72</samp>’, ‘<samp class="samp">cortex-a73</samp>’, ‘<samp class="samp">cortex-a75</samp>’, ‘<samp class="samp">cortex-a76</samp>’, ‘<samp class="samp">cortex-a76ae</samp>’, ‘<samp class="samp">cortex-a77</samp>’, ‘<samp class="samp">cortex-a78</samp>’, ‘<samp class="samp">cortex-a78ae</samp>’, ‘<samp class="samp">cortex-a78c</samp>’, ‘<samp class="samp">cortex-a710</samp>’, ‘<samp class="samp">ares</samp>’, ‘<samp class="samp">cortex-r4</samp>’, ‘<samp class="samp">cortex-r4f</samp>’, ‘<samp class="samp">cortex-r5</samp>’, ‘<samp class="samp">cortex-r7</samp>’, ‘<samp class="samp">cortex-r8</samp>’, ‘<samp class="samp">cortex-r52</samp>’, ‘<samp class="samp">cortex-r52plus</samp>’, ‘<samp class="samp">cortex-m0</samp>’, ‘<samp class="samp">cortex-m0plus</samp>’, ‘<samp class="samp">cortex-m1</samp>’, ‘<samp class="samp">cortex-m3</samp>’, ‘<samp class="samp">cortex-m4</samp>’, ‘<samp class="samp">cortex-m7</samp>’, ‘<samp class="samp">cortex-m23</samp>’, ‘<samp class="samp">cortex-m33</samp>’, ‘<samp class="samp">cortex-m35p</samp>’, ‘<samp class="samp">cortex-m55</samp>’, ‘<samp class="samp">cortex-m85</samp>’, ‘<samp class="samp">cortex-x1</samp>’, ‘<samp class="samp">cortex-x1c</samp>’, ‘<samp class="samp">cortex-m1.small-multiply</samp>’, ‘<samp class="samp">cortex-m0.small-multiply</samp>’, ‘<samp class="samp">cortex-m0plus.small-multiply</samp>’, ‘<samp class="samp">exynos-m1</samp>’, ‘<samp class="samp">marvell-pj4</samp>’, ‘<samp class="samp">neoverse-n1</samp>’, ‘<samp class="samp">neoverse-n2</samp>’, ‘<samp class="samp">neoverse-v1</samp>’, ‘<samp class="samp">xscale</samp>’, ‘<samp class="samp">iwmmxt</samp>’, ‘<samp class="samp">iwmmxt2</samp>’, ‘<samp class="samp">ep9312</samp>’, ‘<samp class="samp">fa526</samp>’, ‘<samp class="samp">fa626</samp>’, ‘<samp class="samp">fa606te</samp>’, ‘<samp class="samp">fa626te</samp>’, ‘<samp class="samp">fmp626</samp>’, ‘<samp class="samp">fa726te</samp>’, ‘<samp class="samp">star-mc1</samp>’, ‘<samp class="samp">xgene1</samp>’. </p> <p>Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: ‘<samp class="samp">cortex-a15.cortex-a7</samp>’, ‘<samp class="samp">cortex-a17.cortex-a7</samp>’, ‘<samp class="samp">cortex-a57.cortex-a53</samp>’, ‘<samp class="samp">cortex-a72.cortex-a53</samp>’, ‘<samp class="samp">cortex-a72.cortex-a35</samp>’, ‘<samp class="samp">cortex-a73.cortex-a53</samp>’, ‘<samp class="samp">cortex-a75.cortex-a55</samp>’, ‘<samp class="samp">cortex-a76.cortex-a55</samp>’. </p> <p><samp class="option">-mtune=generic-<var class="var">arch</var></samp> specifies that GCC should tune the performance for a blend of processors within architecture <var class="var">arch</var>. The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go. </p> <p><samp class="option">-mtune</samp> permits the same extension options as <samp class="option">-mcpu</samp>, but the extension options do not affect the tuning of the generated code. </p> <p><samp class="option">-mtune=native</samp> causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. </p> </dd> <dt>
<span><code class="code">-mcpu=<var class="var">name</var><span class="r">[</span>+extension…<span class="r">]</span></code><a class="copiable-link" href="#index-mcpu-2"> ¶</a></span>
</dt> <dd>
<p>This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified by <samp class="option">-march</samp>) and the ARM processor type for which to tune for performance (as if specified by <samp class="option">-mtune</samp>). Where this option is used in conjunction with <samp class="option">-march</samp> or <samp class="option">-mtune</samp>, those options take precedence over the appropriate part of this option. </p> <p>Many of the supported CPUs implement optional architectural extensions. Where this is so the architectural extensions are normally enabled by default. If implementations that lack the extension exist, then the extension syntax can be used to disable those extensions that have been omitted. For floating-point and Advanced SIMD (Neon) instructions, the settings of the options <samp class="option">-mfloat-abi</samp> and <samp class="option">-mfpu</samp> must also be considered: floating-point and Advanced SIMD instructions will only be used if <samp class="option">-mfloat-abi</samp> is not set to ‘<samp class="samp">soft</samp>’; and any setting of <samp class="option">-mfpu</samp> other than ‘<samp class="samp">auto</samp>’ will override the available floating-point and SIMD extension instructions. </p> <p>For example, ‘<samp class="samp">cortex-a9</samp>’ can be found in three major configurations: integer only, with just a floating-point unit or with floating-point and Advanced SIMD. The default is to enable all the instructions, but the extensions ‘<samp class="samp">+nosimd</samp>’ and ‘<samp class="samp">+nofp</samp>’ can be used to disable just the SIMD or both the SIMD and floating-point instructions respectively. </p> <p>Permissible names for this option are the same as those for <samp class="option">-mtune</samp>. </p> <p>The following extension options are common to the listed CPUs: </p> <dl class="table"> <dt>‘<samp class="samp">+nodsp</samp>’</dt> <dd>
<p>Disable the DSP instructions on ‘<samp class="samp">cortex-m33</samp>’, ‘<samp class="samp">cortex-m35p</samp>’, ‘<samp class="samp">cortex-m55</samp>’ and ‘<samp class="samp">cortex-m85</samp>’. Also disable the M-Profile Vector Extension (MVE) integer and single precision floating-point instructions on ‘<samp class="samp">cortex-m55</samp>’ and ‘<samp class="samp">cortex-m85</samp>’. </p> </dd> <dt>‘<samp class="samp">+nopacbti</samp>’</dt> <dd>
<p>Disable the Pointer Authentication and Branch Target Identification Extension on ‘<samp class="samp">cortex-m85</samp>’. </p> </dd> <dt>‘<samp class="samp">+nomve</samp>’</dt> <dd>
<p>Disable the M-Profile Vector Extension (MVE) integer and single precision floating-point instructions on ‘<samp class="samp">cortex-m55</samp>’ and ‘<samp class="samp">cortex-m85</samp>’. </p> </dd> <dt>‘<samp class="samp">+nomve.fp</samp>’</dt> <dd>
<p>Disable the M-Profile Vector Extension (MVE) single precision floating-point instructions on ‘<samp class="samp">cortex-m55</samp>’ and ‘<samp class="samp">cortex-m85</samp>’. </p> </dd> <dt>‘<samp class="samp">+cdecp0, +cdecp1, ... , +cdecp7</samp>’</dt> <dd>
<p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7 on ‘<samp class="samp">cortex-m55</samp>’. </p> </dd> <dt>‘<samp class="samp">+nofp</samp>’</dt> <dd>
<p>Disables the floating-point instructions on ‘<samp class="samp">arm9e</samp>’, ‘<samp class="samp">arm946e-s</samp>’, ‘<samp class="samp">arm966e-s</samp>’, ‘<samp class="samp">arm968e-s</samp>’, ‘<samp class="samp">arm10e</samp>’, ‘<samp class="samp">arm1020e</samp>’, ‘<samp class="samp">arm1022e</samp>’, ‘<samp class="samp">arm926ej-s</samp>’, ‘<samp class="samp">arm1026ej-s</samp>’, ‘<samp class="samp">cortex-r5</samp>’, ‘<samp class="samp">cortex-r7</samp>’, ‘<samp class="samp">cortex-r8</samp>’, ‘<samp class="samp">cortex-m4</samp>’, ‘<samp class="samp">cortex-m7</samp>’, ‘<samp class="samp">cortex-m33</samp>’, ‘<samp class="samp">cortex-m35p</samp>’ ‘<samp class="samp">cortex-m4</samp>’, ‘<samp class="samp">cortex-m7</samp>’, ‘<samp class="samp">cortex-m33</samp>’, ‘<samp class="samp">cortex-m35p</samp>’, ‘<samp class="samp">cortex-m55</samp>’ and ‘<samp class="samp">cortex-m85</samp>’. Disables the floating-point and SIMD instructions on ‘<samp class="samp">generic-armv7-a</samp>’, ‘<samp class="samp">cortex-a5</samp>’, ‘<samp class="samp">cortex-a7</samp>’, ‘<samp class="samp">cortex-a8</samp>’, ‘<samp class="samp">cortex-a9</samp>’, ‘<samp class="samp">cortex-a12</samp>’, ‘<samp class="samp">cortex-a15</samp>’, ‘<samp class="samp">cortex-a17</samp>’, ‘<samp class="samp">cortex-a15.cortex-a7</samp>’, ‘<samp class="samp">cortex-a17.cortex-a7</samp>’, ‘<samp class="samp">cortex-a32</samp>’, ‘<samp class="samp">cortex-a35</samp>’, ‘<samp class="samp">cortex-a53</samp>’ and ‘<samp class="samp">cortex-a55</samp>’. </p> </dd> <dt>‘<samp class="samp">+nofp.dp</samp>’</dt> <dd>
<p>Disables the double-precision component of the floating-point instructions on ‘<samp class="samp">cortex-r5</samp>’, ‘<samp class="samp">cortex-r7</samp>’, ‘<samp class="samp">cortex-r8</samp>’, ‘<samp class="samp">cortex-r52</samp>’, ‘<samp class="samp">cortex-r52plus</samp>’ and ‘<samp class="samp">cortex-m7</samp>’. </p> </dd> <dt>‘<samp class="samp">+nosimd</samp>’</dt> <dd>
<p>Disables the SIMD (but not floating-point) instructions on ‘<samp class="samp">generic-armv7-a</samp>’, ‘<samp class="samp">cortex-a5</samp>’, ‘<samp class="samp">cortex-a7</samp>’ and ‘<samp class="samp">cortex-a9</samp>’. </p> </dd> <dt>‘<samp class="samp">+crypto</samp>’</dt> <dd><p>Enables the cryptographic instructions on ‘<samp class="samp">cortex-a32</samp>’, ‘<samp class="samp">cortex-a35</samp>’, ‘<samp class="samp">cortex-a53</samp>’, ‘<samp class="samp">cortex-a55</samp>’, ‘<samp class="samp">cortex-a57</samp>’, ‘<samp class="samp">cortex-a72</samp>’, ‘<samp class="samp">cortex-a73</samp>’, ‘<samp class="samp">cortex-a75</samp>’, ‘<samp class="samp">exynos-m1</samp>’, ‘<samp class="samp">xgene1</samp>’, ‘<samp class="samp">cortex-a57.cortex-a53</samp>’, ‘<samp class="samp">cortex-a72.cortex-a53</samp>’, ‘<samp class="samp">cortex-a73.cortex-a35</samp>’, ‘<samp class="samp">cortex-a73.cortex-a53</samp>’ and ‘<samp class="samp">cortex-a75.cortex-a55</samp>’. </p></dd> </dl> <p>Additionally the ‘<samp class="samp">generic-armv7-a</samp>’ pseudo target defaults to VFPv3 with 16 double-precision registers. It supports the following extension options: ‘<samp class="samp">mp</samp>’, ‘<samp class="samp">sec</samp>’, ‘<samp class="samp">vfpv3-d16</samp>’, ‘<samp class="samp">vfpv3</samp>’, ‘<samp class="samp">vfpv3-d16-fp16</samp>’, ‘<samp class="samp">vfpv3-fp16</samp>’, ‘<samp class="samp">vfpv4-d16</samp>’, ‘<samp class="samp">vfpv4</samp>’, ‘<samp class="samp">neon</samp>’, ‘<samp class="samp">neon-vfpv3</samp>’, ‘<samp class="samp">neon-fp16</samp>’, ‘<samp class="samp">neon-vfpv4</samp>’. The meanings are the same as for the extensions to <samp class="option">-march=armv7-a</samp>. </p> <p><samp class="option">-mcpu=generic-<var class="var">arch</var></samp> is also permissible, and is equivalent to <samp class="option">-march=<var class="var">arch</var> -mtune=generic-<var class="var">arch</var></samp>. See <samp class="option">-mtune</samp> for more information. </p> <p><samp class="option">-mcpu=native</samp> causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. </p> </dd> <dt>
<span><code class="code">-mfpu=<var class="var">name</var></code><a class="copiable-link" href="#index-mfpu-1"> ¶</a></span>
</dt> <dd>
<p>This specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: ‘<samp class="samp">auto</samp>’, ‘<samp class="samp">vfpv2</samp>’, ‘<samp class="samp">vfpv3</samp>’, ‘<samp class="samp">vfpv3-fp16</samp>’, ‘<samp class="samp">vfpv3-d16</samp>’, ‘<samp class="samp">vfpv3-d16-fp16</samp>’, ‘<samp class="samp">vfpv3xd</samp>’, ‘<samp class="samp">vfpv3xd-fp16</samp>’, ‘<samp class="samp">neon-vfpv3</samp>’, ‘<samp class="samp">neon-fp16</samp>’, ‘<samp class="samp">vfpv4</samp>’, ‘<samp class="samp">vfpv4-d16</samp>’, ‘<samp class="samp">fpv4-sp-d16</samp>’, ‘<samp class="samp">neon-vfpv4</samp>’, ‘<samp class="samp">fpv5-d16</samp>’, ‘<samp class="samp">fpv5-sp-d16</samp>’, ‘<samp class="samp">fp-armv8</samp>’, ‘<samp class="samp">neon-fp-armv8</samp>’ and ‘<samp class="samp">crypto-neon-fp-armv8</samp>’. Note that ‘<samp class="samp">neon</samp>’ is an alias for ‘<samp class="samp">neon-vfpv3</samp>’ and ‘<samp class="samp">vfp</samp>’ is an alias for ‘<samp class="samp">vfpv2</samp>’. </p> <p>The setting ‘<samp class="samp">auto</samp>’ is the default and is special. It causes the compiler to select the floating-point and Advanced SIMD instructions based on the settings of <samp class="option">-mcpu</samp> and <samp class="option">-march</samp>. </p> <p>If the selected floating-point hardware includes the NEON extension (e.g. <samp class="option">-mfpu=neon</samp>), note that floating-point operations are not generated by GCC’s auto-vectorization pass unless <samp class="option">-funsafe-math-optimizations</samp> is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision. </p> <p>You can also set the fpu name at function level by using the <code class="code">target("fpu=")</code> function attributes (see <a class="pxref" href="arm-function-attributes">ARM Function Attributes</a>) or pragmas (see <a class="pxref" href="function-specific-option-pragmas">Function Specific Option Pragmas</a>). </p> </dd> <dt>
<span><code class="code">-mfp16-format=<var class="var">name</var></code><a class="copiable-link" href="#index-mfp16-format"> ¶</a></span>
</dt> <dd>
<p>Specify the format of the <code class="code">__fp16</code> half-precision floating-point type. Permissible names are ‘<samp class="samp">none</samp>’, ‘<samp class="samp">ieee</samp>’, and ‘<samp class="samp">alternative</samp>’; the default is ‘<samp class="samp">none</samp>’, in which case the <code class="code">__fp16</code> type is not defined. See <a class="xref" href="half-precision">Half-Precision Floating Point</a>, for more information. </p> </dd> <dt>
<span><code class="code">-mstructure-size-boundary=<var class="var">n</var></code><a class="copiable-link" href="#index-mstructure-size-boundary"> ¶</a></span>
</dt> <dd>
<p>The sizes of all structures and unions are rounded up to a multiple of the number of bits set by this option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI supports it. </p> <p>Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions. </p> <p>This option is deprecated. </p> </dd> <dt>
<span><code class="code">-mabort-on-noreturn</code><a class="copiable-link" href="#index-mabort-on-noreturn"> ¶</a></span>
</dt> <dd>
<p>Generate a call to the function <code class="code">abort</code> at the end of a <code class="code">noreturn</code> function. It is executed if the function tries to return. </p> </dd> <dt>
 <span><code class="code">-mlong-calls</code><a class="copiable-link" href="#index-mlong-calls-2"> ¶</a></span>
</dt> <dt><code class="code">-mno-long-calls</code></dt> <dd>
<p>Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction. </p> <p>Even if this switch is enabled, not all function calls are turned into long calls. The heuristic is that static functions, functions that have the <code class="code">short_call</code> attribute, functions that are inside the scope of a <code class="code">#pragma no_long_calls</code> directive, and functions whose definitions have already been compiled within the current compilation unit are not turned into long calls. The exceptions to this rule are that weak function definitions, functions with the <code class="code">long_call</code> attribute or the <code class="code">section</code> attribute, and functions that are within the scope of a <code class="code">#pragma long_calls</code> directive are always turned into long calls. </p> <p>This feature is not enabled by default. Specifying <samp class="option">-mno-long-calls</samp> restores the default behavior, as does placing the function calls within the scope of a <code class="code">#pragma
long_calls_off</code> directive. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers. </p> </dd> <dt>
<span><code class="code">-msingle-pic-base</code><a class="copiable-link" href="#index-msingle-pic-base"> ¶</a></span>
</dt> <dd>
<p>Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins. </p> </dd> <dt>
<span><code class="code">-mpic-register=<var class="var">reg</var></code><a class="copiable-link" href="#index-mpic-register"> ¶</a></span>
</dt> <dd>
<p>Specify the register to be used for PIC addressing. For standard PIC base case, the default is any suitable register determined by compiler. For single PIC base case, the default is ‘<samp class="samp">R9</samp>’ if target is EABI based or stack-checking is enabled, otherwise the default is ‘<samp class="samp">R10</samp>’. </p> </dd> <dt>
<span><code class="code">-mpic-data-is-text-relative</code><a class="copiable-link" href="#index-mpic-data-is-text-relative"> ¶</a></span>
</dt> <dd>
<p>Assume that the displacement between the text and data segments is fixed at static link time. This permits using PC-relative addressing operations to access data known to be in the data segment. For non-VxWorks RTP targets, this option is enabled by default. When disabled on such targets, it will enable <samp class="option">-msingle-pic-base</samp> by default. </p> </dd> <dt>
<span><code class="code">-mpoke-function-name</code><a class="copiable-link" href="#index-mpoke-function-name"> ¶</a></span>
</dt> <dd>
<p>Write the name of each function into the text section, directly preceding the function prologue. The generated code is similar to this: </p> <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">t0
    .ascii "arm_poke_function_name", 0
    .align
t1
    .word 0xff000000 + (t1 - t0)
arm_poke_function_name
    mov     ip, sp
    stmfd   sp!, {fp, ip, lr, pc}
    sub     fp, ip, #4</pre>
</div> <p>When performing a stack backtrace, code can inspect the value of <code class="code">pc</code> stored at <code class="code">fp + 0</code>. If the trace function then looks at location <code class="code">pc - 12</code> and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length <code class="code">((pc[-3]) &amp; 0xff000000)</code>. </p> </dd> <dt>
 <span><code class="code">-mthumb</code><a class="copiable-link" href="#index-marm"> ¶</a></span>
</dt> <dt><code class="code">-marm</code></dt> <dd> <p>Select between generating code that executes in ARM and Thumb states. The default for most configurations is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the <samp class="option">--with-mode=</samp><var class="var">state</var> configure option. </p> <p>You can also override the ARM and Thumb mode for each function by using the <code class="code">target("thumb")</code> and <code class="code">target("arm")</code> function attributes (see <a class="pxref" href="arm-function-attributes">ARM Function Attributes</a>) or pragmas (see <a class="pxref" href="function-specific-option-pragmas">Function Specific Option Pragmas</a>). </p> </dd> <dt>
<span><code class="code">-mflip-thumb</code><a class="copiable-link" href="#index-mflip-thumb"> ¶</a></span>
</dt> <dd>
<p>Switch ARM/Thumb modes on alternating functions. This option is provided for regression testing of mixed Thumb/ARM code generation, and is not intended for ordinary use in compiling code. </p> </dd> <dt>
<span><code class="code">-mtpcs-frame</code><a class="copiable-link" href="#index-mtpcs-frame"> ¶</a></span>
</dt> <dd>
<p>Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions. (A leaf function is one that does not call any other functions.) The default is <samp class="option">-mno-tpcs-frame</samp>. </p> </dd> <dt>
<span><code class="code">-mtpcs-leaf-frame</code><a class="copiable-link" href="#index-mtpcs-leaf-frame"> ¶</a></span>
</dt> <dd>
<p>Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A leaf function is one that does not call any other functions.) The default is <samp class="option">-mno-apcs-leaf-frame</samp>. </p> </dd> <dt>
<span><code class="code">-mcallee-super-interworking</code><a class="copiable-link" href="#index-mcallee-super-interworking"> ¶</a></span>
</dt> <dd>
<p>Gives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function. This allows these functions to be called from non-interworking code. This option is not valid in AAPCS configurations because interworking is enabled by default. </p> </dd> <dt>
<span><code class="code">-mcaller-super-interworking</code><a class="copiable-link" href="#index-mcaller-super-interworking"> ¶</a></span>
</dt> <dd>
<p>Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not. There is a small overhead in the cost of executing a function pointer if this option is enabled. This option is not valid in AAPCS configurations because interworking is enabled by default. </p> </dd> <dt>
<span><code class="code">-mtp=<var class="var">name</var></code><a class="copiable-link" href="#index-mtp"> ¶</a></span>
</dt> <dd>
<p>Specify the access model for the thread local storage pointer. The valid models are ‘<samp class="samp">soft</samp>’, which generates calls to <code class="code">__aeabi_read_tp</code>, ‘<samp class="samp">cp15</samp>’, which fetches the thread pointer from <code class="code">cp15</code> directly (supported in the arm6k architecture), and ‘<samp class="samp">auto</samp>’, which uses the best available method for the selected processor. The default setting is ‘<samp class="samp">auto</samp>’. </p> </dd> <dt>
<span><code class="code">-mtls-dialect=<var class="var">dialect</var></code><a class="copiable-link" href="#index-mtls-dialect"> ¶</a></span>
</dt> <dd>
<p>Specify the dialect to use for accessing thread local storage. Two <var class="var">dialect</var>s are supported—‘<samp class="samp">gnu</samp>’ and ‘<samp class="samp">gnu2</samp>’. The ‘<samp class="samp">gnu</samp>’ dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The ‘<samp class="samp">gnu2</samp>’ dialect selects the GNU descriptor scheme, which provides better performance for shared libraries. The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support. Initial and local exec TLS models are unaffected by this option and always use the original scheme. </p> </dd> <dt>
<span><code class="code">-mword-relocations</code><a class="copiable-link" href="#index-mword-relocations"> ¶</a></span>
</dt> <dd>
<p>Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when <samp class="option">-fpic</samp> or <samp class="option">-fPIC</samp> is specified. This option conflicts with <samp class="option">-mslow-flash-data</samp>. </p> </dd> <dt>
<span><code class="code">-mfix-cortex-m3-ldrd</code><a class="copiable-link" href="#index-mfix-cortex-m3-ldrd"> ¶</a></span>
</dt> <dd>
<p>Some Cortex-M3 cores can cause data corruption when <code class="code">ldrd</code> instructions with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when <samp class="option">-mcpu=cortex-m3</samp> is specified. </p> </dd> <dt><code class="code">-mfix-cortex-a57-aes-1742098</code></dt> <dt><code class="code">-mno-fix-cortex-a57-aes-1742098</code></dt> <dt><code class="code">-mfix-cortex-a72-aes-1655431</code></dt> <dt><code class="code">-mno-fix-cortex-a72-aes-1655431</code></dt> <dd>
<p>Enable (disable) mitigation for an erratum on Cortex-A57 and Cortex-A72 that affects the AES cryptographic instructions. This option is enabled by default when either <samp class="option">-mcpu=cortex-a57</samp> or <samp class="option">-mcpu=cortex-a72</samp> is specified. </p> </dd> <dt>
 <span><code class="code">-munaligned-access</code><a class="copiable-link" href="#index-munaligned-access"> ¶</a></span>
</dt> <dt><code class="code">-mno-unaligned-access</code></dt> <dd>
<p>Enables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32- bit aligned. By default unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for ARMv8-M Baseline architectures, and enabled for all other architectures. If unaligned access is not enabled then words in packed data structures are accessed a byte at a time. </p> <p>The ARM attribute <code class="code">Tag_CPU_unaligned_access</code> is set in the generated object file to either true or false, depending upon the setting of this option. If unaligned access is enabled then the preprocessor symbol <code class="code">__ARM_FEATURE_UNALIGNED</code> is also defined. </p> </dd> <dt>
<span><code class="code">-mneon-for-64bits</code><a class="copiable-link" href="#index-mneon-for-64bits"> ¶</a></span>
</dt> <dd>
<p>This option is deprecated and has no effect. </p> </dd> <dt>
<span><code class="code">-mslow-flash-data</code><a class="copiable-link" href="#index-mslow-flash-data"> ¶</a></span>
</dt> <dd>
<p>Assume loading data from flash is slower than fetching instruction. Therefore literal load is minimized for better performance. This option is only supported when compiling for ARMv7 M-profile and off by default. It conflicts with <samp class="option">-mword-relocations</samp>. </p> </dd> <dt>
<span><code class="code">-masm-syntax-unified</code><a class="copiable-link" href="#index-masm-syntax-unified"> ¶</a></span>
</dt> <dd>
<p>Assume inline assembler is using unified asm syntax. The default is currently off which implies divided syntax. This option has no impact on Thumb2. However, this may change in future releases of GCC. Divided syntax should be considered deprecated. </p> </dd> <dt>
<span><code class="code">-mrestrict-it</code><a class="copiable-link" href="#index-mrestrict-it"> ¶</a></span>
</dt> <dd>
<p>Restricts generation of IT blocks to conform to the rules of ARMv8-A. IT blocks can only contain a single 16-bit instruction from a select set of instructions. This option is on by default for ARMv8-A Thumb mode. </p> </dd> <dt>
<span><code class="code">-mprint-tune-info</code><a class="copiable-link" href="#index-mprint-tune-info"> ¶</a></span>
</dt> <dd>
<p>Print CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code. This option is disabled by default. </p> </dd> <dt>
<span><code class="code">-mverbose-cost-dump</code><a class="copiable-link" href="#index-mverbose-cost-dump-1"> ¶</a></span>
</dt> <dd>
<p>Enable verbose cost model dumping in the debug dump files. This option is provided for use in debugging the compiler. </p> </dd> <dt>
<span><code class="code">-mpure-code</code><a class="copiable-link" href="#index-mpure-code"> ¶</a></span>
</dt> <dd>
<p>Do not allow constant data to be placed in code sections. Additionally, when compiling for ELF object format give all text sections the ELF processor-specific section attribute <code class="code">SHF_ARM_PURECODE</code>. This option is only available when generating non-pic code for M-profile targets. </p> </dd> <dt>
<span><code class="code">-mcmse</code><a class="copiable-link" href="#index-mcmse"> ¶</a></span>
</dt> <dd>
<p>Generate secure code as per the "ARMv8-M Security Extensions: Requirements on Development Tools Engineering Specification", which can be found on <a class="url" href="https://developer.arm.com/documentation/ecm0359818/latest/">https://developer.arm.com/documentation/ecm0359818/latest/</a>. </p> </dd> <dt>
<span><code class="code">-mfix-cmse-cve-2021-35465</code><a class="copiable-link" href="#index-mfix-cmse-cve-2021-35465"> ¶</a></span>
</dt> <dd>
<p>Mitigate against a potential security issue with the <code class="code">VLLDM</code> instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option <samp class="option">-mcpu=</samp> is used with <code class="code">cortex-m33</code>, <code class="code">cortex-m35p</code>, <code class="code">cortex-m55</code>, <code class="code">cortex-m85</code> or <code class="code">star-mc1</code>. The option <samp class="option">-mno-fix-cmse-cve-2021-35465</samp> can be used to disable the mitigation. </p> </dd> <dt>
 <span><code class="code">-mstack-protector-guard=<var class="var">guard</var></code><a class="copiable-link" href="#index-mstack-protector-guard-1"> ¶</a></span>
</dt> <dt><code class="code">-mstack-protector-guard-offset=<var class="var">offset</var></code></dt> <dd>
<p>Generate stack protection code using canary at <var class="var">guard</var>. Supported locations are ‘<samp class="samp">global</samp>’ for a global canary or ‘<samp class="samp">tls</samp>’ for a canary accessible via the TLS register. The option <samp class="option">-mstack-protector-guard-offset=</samp> is for use with <samp class="option">-fstack-protector-guard=tls</samp> and not for use in user-land code. </p> </dd> <dt>
 <span><code class="code">-mfdpic</code><a class="copiable-link" href="#index-mfdpic"> ¶</a></span>
</dt> <dt><code class="code">-mno-fdpic</code></dt> <dd>
<p>Select the FDPIC ABI, which uses 64-bit function descriptors to represent pointers to functions. When the compiler is configured for <code class="code">arm-*-uclinuxfdpiceabi</code> targets, this option is on by default and implies <samp class="option">-fPIE</samp> if none of the PIC/PIE-related options is provided. On other targets, it only enables the FDPIC-specific code generation features, and the user should explicitly provide the PIC/PIE-related options as needed. </p> <p>Note that static linking is not supported because it would still involve the dynamic linker when the program self-relocates. If such behavior is acceptable, use -static and -Wl,-dynamic-linker options. </p> <p>The opposite <samp class="option">-mno-fdpic</samp> option is useful (and required) to build the Linux kernel using the same (<code class="code">arm-*-uclinuxfdpiceabi</code>) toolchain as the one used to build the userland programs. </p> </dd> <dt>
<span><code class="code">-mbranch-protection=<var class="var">none</var>|<var class="var">standard</var>|<var class="var">pac-ret</var>[+<var class="var">leaf</var>][+<var class="var">bti</var>]|<var class="var">bti</var>[+<var class="var">pac-ret</var>[+<var class="var">leaf</var>]]</code><a class="copiable-link" href="#index-mbranch-protection-1"> ¶</a></span>
</dt> <dd>
<p>Enable branch protection features (armv8.1-m.main only). ‘<samp class="samp">none</samp>’ generate code without branch protection or return address signing. ‘<samp class="samp">standard[+<var class="var">leaf</var>]</samp>’ generate code with all branch protection features enabled at their standard level. ‘<samp class="samp">pac-ret[+<var class="var">leaf</var>]</samp>’ generate code with return address signing set to its standard level, which is to sign all functions that save the return address to memory. ‘<samp class="samp">leaf</samp>’ When return address signing is enabled, also sign leaf functions even if they do not write the return address to memory. +‘<samp class="samp">bti</samp>’ Add landing-pad instructions at the permitted targets of indirect branch instructions. </p> <p>If the ‘<samp class="samp">+pacbti</samp>’ architecture extension is not enabled, then all branch protection and return address signing operations are constrained to use only the instructions defined in the architectural-NOP space. The generated code will remain backwards-compatible with earlier versions of the architecture, but the additional security can be enabled at run time on processors that support the ‘<samp class="samp">PACBTI</samp>’ extension. </p> <p>Branch target enforcement using BTI can only be enabled at runtime if all code in the application has been compiled with at least ‘<samp class="samp">-mbranch-protection=bti</samp>’. </p> <p>Any setting other than ‘<samp class="samp">none</samp>’ is supported only on armv8-m.main or later. </p> <p>The default is to generate code without branch protection or return address signing. </p> </dd> </dl> </div>  <div class="nav-panel"> <p> Next: <a href="avr-options">AVR Options</a>, Previous: <a href="arc-options">ARC Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
  <p class="_attribution-p">
    &copy; Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
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