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<div class="subsubsection-level-extent" id="Basic-PowerPC-Built-in-Functions-Available-on-all-Configurations"> <div class="nav-panel"> <p> Next: <a href="basic-powerpc-built-in-functions-available-on-isa-2_002e05" accesskey="n" rel="next">Basic PowerPC Built-in Functions Available on ISA 2.05</a>, Up: <a href="basic-powerpc-built-in-functions" accesskey="u" rel="up">Basic PowerPC Built-in Functions</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div> <h1 class="subsubsection" id="Basic-PowerPC-Built-in-Functions-Available-on-all-Configurations-1"><span>6.60.22.1 Basic PowerPC Built-in Functions Available on all Configurations<a class="copiable-link" href="#Basic-PowerPC-Built-in-Functions-Available-on-all-Configurations-1"> ¶</a></span></h1> <dl class="first-deftypefn"> <dt class="deftypefn" id="index-_005f_005fbuiltin_005fcpu_005finit">
<span class="category-def">Built-in Function: </span><span><code class="def-type">void</code> <strong class="def-name">__builtin_cpu_init</strong> <code class="def-code-arguments">(void)</code><a class="copiable-link" href="#index-_005f_005fbuiltin_005fcpu_005finit"> ¶</a></span>
</dt> <dd><p>This function is a <code class="code">nop</code> on the PowerPC platform and is included solely to maintain API compatibility with the x86 builtins. </p></dd>
</dl> <dl class="first-deftypefn"> <dt class="deftypefn" id="index-_005f_005fbuiltin_005fcpu_005fis">
<span class="category-def">Built-in Function: </span><span><code class="def-type">int</code> <strong class="def-name">__builtin_cpu_is</strong> <code class="def-code-arguments">(const char *<var class="var">cpuname</var>)</code><a class="copiable-link" href="#index-_005f_005fbuiltin_005fcpu_005fis"> ¶</a></span>
</dt> <dd>
<p>This function returns a value of <code class="code">1</code> if the run-time CPU is of type <var class="var">cpuname</var> and returns <code class="code">0</code> otherwise </p> <p>The <code class="code">__builtin_cpu_is</code> function requires GLIBC 2.23 or newer which exports the hardware capability bits. GCC defines the macro <code class="code">__BUILTIN_CPU_SUPPORTS__</code> if the <code class="code">__builtin_cpu_supports</code> built-in function is fully supported. </p> <p>If GCC was configured to use a GLIBC before 2.23, the built-in function <code class="code">__builtin_cpu_is</code> always returns a 0 and the compiler issues a warning. </p> <p>The following CPU names can be detected: </p> <dl class="table"> <dt>‘<samp class="samp">power10</samp>’</dt> <dd><p>IBM POWER10 Server CPU. </p></dd> <dt>‘<samp class="samp">power9</samp>’</dt> <dd><p>IBM POWER9 Server CPU. </p></dd> <dt>‘<samp class="samp">power8</samp>’</dt> <dd><p>IBM POWER8 Server CPU. </p></dd> <dt>‘<samp class="samp">power7</samp>’</dt> <dd><p>IBM POWER7 Server CPU. </p></dd> <dt>‘<samp class="samp">power6x</samp>’</dt> <dd><p>IBM POWER6 Server CPU (RAW mode). </p></dd> <dt>‘<samp class="samp">power6</samp>’</dt> <dd><p>IBM POWER6 Server CPU (Architected mode). </p></dd> <dt>‘<samp class="samp">power5+</samp>’</dt> <dd><p>IBM POWER5+ Server CPU. </p></dd> <dt>‘<samp class="samp">power5</samp>’</dt> <dd><p>IBM POWER5 Server CPU. </p></dd> <dt>‘<samp class="samp">ppc970</samp>’</dt> <dd><p>IBM 970 Server CPU (ie, Apple G5). </p></dd> <dt>‘<samp class="samp">power4</samp>’</dt> <dd><p>IBM POWER4 Server CPU. </p></dd> <dt>‘<samp class="samp">ppca2</samp>’</dt> <dd><p>IBM A2 64-bit Embedded CPU </p></dd> <dt>‘<samp class="samp">ppc476</samp>’</dt> <dd><p>IBM PowerPC 476FP 32-bit Embedded CPU. </p></dd> <dt>‘<samp class="samp">ppc464</samp>’</dt> <dd><p>IBM PowerPC 464 32-bit Embedded CPU. </p></dd> <dt>‘<samp class="samp">ppc440</samp>’</dt> <dd><p>PowerPC 440 32-bit Embedded CPU. </p></dd> <dt>‘<samp class="samp">ppc405</samp>’</dt> <dd><p>PowerPC 405 32-bit Embedded CPU. </p></dd> <dt>‘<samp class="samp">ppc-cell-be</samp>’</dt> <dd><p>IBM PowerPC Cell Broadband Engine Architecture CPU. </p></dd> </dl> <p>Here is an example: </p>
<div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">#ifdef __BUILTIN_CPU_SUPPORTS__
if (__builtin_cpu_is ("power8"))
{
do_power8 (); // POWER8 specific implementation.
}
else
#endif
{
do_generic (); // Generic implementation.
}</pre>
</div> </dd>
</dl> <dl class="first-deftypefn"> <dt class="deftypefn" id="index-_005f_005fbuiltin_005fcpu_005fsupports">
<span class="category-def">Built-in Function: </span><span><code class="def-type">int</code> <strong class="def-name">__builtin_cpu_supports</strong> <code class="def-code-arguments">(const char *<var class="var">feature</var>)</code><a class="copiable-link" href="#index-_005f_005fbuiltin_005fcpu_005fsupports"> ¶</a></span>
</dt> <dd>
<p>This function returns a value of <code class="code">1</code> if the run-time CPU supports the HWCAP feature <var class="var">feature</var> and returns <code class="code">0</code> otherwise. </p> <p>The <code class="code">__builtin_cpu_supports</code> function requires GLIBC 2.23 or newer which exports the hardware capability bits. GCC defines the macro <code class="code">__BUILTIN_CPU_SUPPORTS__</code> if the <code class="code">__builtin_cpu_supports</code> built-in function is fully supported. </p> <p>If GCC was configured to use a GLIBC before 2.23, the built-in function <code class="code">__builtin_cpu_supports</code> always returns a 0 and the compiler issues a warning. </p> <p>The following features can be detected: </p> <dl class="table"> <dt>‘<samp class="samp">4xxmac</samp>’</dt> <dd><p>4xx CPU has a Multiply Accumulator. </p></dd> <dt>‘<samp class="samp">altivec</samp>’</dt> <dd><p>CPU has a SIMD/Vector Unit. </p></dd> <dt>‘<samp class="samp">arch_2_05</samp>’</dt> <dd><p>CPU supports ISA 2.05 (eg, POWER6) </p></dd> <dt>‘<samp class="samp">arch_2_06</samp>’</dt> <dd><p>CPU supports ISA 2.06 (eg, POWER7) </p></dd> <dt>‘<samp class="samp">arch_2_07</samp>’</dt> <dd><p>CPU supports ISA 2.07 (eg, POWER8) </p></dd> <dt>‘<samp class="samp">arch_3_00</samp>’</dt> <dd><p>CPU supports ISA 3.0 (eg, POWER9) </p></dd> <dt>‘<samp class="samp">arch_3_1</samp>’</dt> <dd><p>CPU supports ISA 3.1 (eg, POWER10) </p></dd> <dt>‘<samp class="samp">archpmu</samp>’</dt> <dd><p>CPU supports the set of compatible performance monitoring events. </p></dd> <dt>‘<samp class="samp">booke</samp>’</dt> <dd><p>CPU supports the Embedded ISA category. </p></dd> <dt>‘<samp class="samp">cellbe</samp>’</dt> <dd><p>CPU has a CELL broadband engine. </p></dd> <dt>‘<samp class="samp">darn</samp>’</dt> <dd><p>CPU supports the <code class="code">darn</code> (deliver a random number) instruction. </p></dd> <dt>‘<samp class="samp">dfp</samp>’</dt> <dd><p>CPU has a decimal floating point unit. </p></dd> <dt>‘<samp class="samp">dscr</samp>’</dt> <dd><p>CPU supports the data stream control register. </p></dd> <dt>‘<samp class="samp">ebb</samp>’</dt> <dd><p>CPU supports event base branching. </p></dd> <dt>‘<samp class="samp">efpdouble</samp>’</dt> <dd><p>CPU has a SPE double precision floating point unit. </p></dd> <dt>‘<samp class="samp">efpsingle</samp>’</dt> <dd><p>CPU has a SPE single precision floating point unit. </p></dd> <dt>‘<samp class="samp">fpu</samp>’</dt> <dd><p>CPU has a floating point unit. </p></dd> <dt>‘<samp class="samp">htm</samp>’</dt> <dd><p>CPU has hardware transaction memory instructions. </p></dd> <dt>‘<samp class="samp">htm-nosc</samp>’</dt> <dd><p>Kernel aborts hardware transactions when a syscall is made. </p></dd> <dt>‘<samp class="samp">htm-no-suspend</samp>’</dt> <dd><p>CPU supports hardware transaction memory but does not support the <code class="code">tsuspend.</code> instruction. </p></dd> <dt>‘<samp class="samp">ic_snoop</samp>’</dt> <dd><p>CPU supports icache snooping capabilities. </p></dd> <dt>‘<samp class="samp">ieee128</samp>’</dt> <dd><p>CPU supports 128-bit IEEE binary floating point instructions. </p></dd> <dt>‘<samp class="samp">isel</samp>’</dt> <dd><p>CPU supports the integer select instruction. </p></dd> <dt>‘<samp class="samp">mma</samp>’</dt> <dd><p>CPU supports the matrix-multiply assist instructions. </p></dd> <dt>‘<samp class="samp">mmu</samp>’</dt> <dd><p>CPU has a memory management unit. </p></dd> <dt>‘<samp class="samp">notb</samp>’</dt> <dd><p>CPU does not have a timebase (eg, 601 and 403gx). </p></dd> <dt>‘<samp class="samp">pa6t</samp>’</dt> <dd><p>CPU supports the PA Semi 6T CORE ISA. </p></dd> <dt>‘<samp class="samp">power4</samp>’</dt> <dd><p>CPU supports ISA 2.00 (eg, POWER4) </p></dd> <dt>‘<samp class="samp">power5</samp>’</dt> <dd><p>CPU supports ISA 2.02 (eg, POWER5) </p></dd> <dt>‘<samp class="samp">power5+</samp>’</dt> <dd><p>CPU supports ISA 2.03 (eg, POWER5+) </p></dd> <dt>‘<samp class="samp">power6x</samp>’</dt> <dd><p>CPU supports ISA 2.05 (eg, POWER6) extended opcodes mffgpr and mftgpr. </p></dd> <dt>‘<samp class="samp">ppc32</samp>’</dt> <dd><p>CPU supports 32-bit mode execution. </p></dd> <dt>‘<samp class="samp">ppc601</samp>’</dt> <dd><p>CPU supports the old POWER ISA (eg, 601) </p></dd> <dt>‘<samp class="samp">ppc64</samp>’</dt> <dd><p>CPU supports 64-bit mode execution. </p></dd> <dt>‘<samp class="samp">ppcle</samp>’</dt> <dd><p>CPU supports a little-endian mode that uses address swizzling. </p></dd> <dt>‘<samp class="samp">scv</samp>’</dt> <dd><p>Kernel supports system call vectored. </p></dd> <dt>‘<samp class="samp">smt</samp>’</dt> <dd><p>CPU support simultaneous multi-threading. </p></dd> <dt>‘<samp class="samp">spe</samp>’</dt> <dd><p>CPU has a signal processing extension unit. </p></dd> <dt>‘<samp class="samp">tar</samp>’</dt> <dd><p>CPU supports the target address register. </p></dd> <dt>‘<samp class="samp">true_le</samp>’</dt> <dd><p>CPU supports true little-endian mode. </p></dd> <dt>‘<samp class="samp">ucache</samp>’</dt> <dd><p>CPU has unified I/D cache. </p></dd> <dt>‘<samp class="samp">vcrypto</samp>’</dt> <dd><p>CPU supports the vector cryptography instructions. </p></dd> <dt>‘<samp class="samp">vsx</samp>’</dt> <dd><p>CPU supports the vector-scalar extension. </p></dd> </dl> <p>Here is an example: </p>
<div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">#ifdef __BUILTIN_CPU_SUPPORTS__
if (__builtin_cpu_supports ("fpu"))
{
asm("fadd %0,%1,%2" : "=d"(dst) : "d"(src1), "d"(src2));
}
else
#endif
{
dst = __fadd (src1, src2); // Software FP addition function.
}</pre>
</div> </dd>
</dl> <p>The following built-in functions are also available on all PowerPC processors: </p>
<div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">uint64_t __builtin_ppc_get_timebase ();
unsigned long __builtin_ppc_mftb ();
double __builtin_unpack_ibm128 (__ibm128, int);
__ibm128 __builtin_pack_ibm128 (double, double);
double __builtin_mffs (void);
void __builtin_mtfsf (const int, double);
void __builtin_mtfsb0 (const int);
void __builtin_mtfsb1 (const int);
void __builtin_set_fpscr_rn (int);</pre>
</div> <p>The <code class="code">__builtin_ppc_get_timebase</code> and <code class="code">__builtin_ppc_mftb</code> functions generate instructions to read the Time Base Register. The <code class="code">__builtin_ppc_get_timebase</code> function may generate multiple instructions and always returns the 64 bits of the Time Base Register. The <code class="code">__builtin_ppc_mftb</code> function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. The <code class="code">__builtin_mffs</code> return the value of the FPSCR register. Note, ISA 3.0 supports the <code class="code">__builtin_mffsl()</code> which permits software to read the control and non-sticky status bits in the FSPCR without the higher latency associated with accessing the sticky status bits. The <code class="code">__builtin_mtfsf</code> takes a constant 8-bit integer field mask and a double precision floating point argument and generates the <code class="code">mtfsf</code> (extended mnemonic) instruction to write new values to selected fields of the FPSCR. The <code class="code">__builtin_mtfsb0</code> and <code class="code">__builtin_mtfsb1</code> take the bit to change as an argument. The valid bit range is between 0 and 31. The builtins map to the <code class="code">mtfsb0</code> and <code class="code">mtfsb1</code> instructions which take the argument and add 32. Hence these instructions only modify the FPSCR[32:63] bits by changing the specified bit to a zero or one respectively. The <code class="code">__builtin_set_fpscr_rn</code> builtin allows changing both of the floating point rounding mode bits. The argument is a 2-bit value. The argument can either be a <code class="code">const int</code> or stored in a variable. The builtin uses the ISA 3.0 instruction <code class="code">mffscrn</code> if available, otherwise it reads the FPSCR, masks the current rounding mode bits out and OR’s in the new value. </p> </div> <div class="nav-panel"> <p> Next: <a href="basic-powerpc-built-in-functions-available-on-isa-2_002e05">Basic PowerPC Built-in Functions Available on ISA 2.05</a>, Up: <a href="basic-powerpc-built-in-functions">Basic PowerPC Built-in Functions</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
<p class="_attribution-p">
© Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
<a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/Basic-PowerPC-Built-in-Functions-Available-on-all-Configurations.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/Basic-PowerPC-Built-in-Functions-Available-on-all-Configurations.html</a>
</p>
</div>
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