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<div class="subsection-level-extent" id="DEC-Alpha-Options"> <div class="nav-panel"> <p> Next: <a href="ebpf-options" accesskey="n" rel="next">eBPF Options</a>, Previous: <a href="darwin-options" accesskey="p" rel="prev">Darwin Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="DEC-Alpha-Options-1"><span>3.19.12 DEC Alpha Options<a class="copiable-link" href="#DEC-Alpha-Options-1"> ¶</a></span></h1> <p>These ‘<samp class="samp">-m</samp>’ options are defined for the DEC Alpha implementations: </p> <dl class="table"> <dt>
 <span><code class="code">-mno-soft-float</code><a class="copiable-link" href="#index-mno-soft-float"> ¶</a></span>
</dt> <dt><code class="code">-msoft-float</code></dt> <dd>
<p>Use (do not use) the hardware floating-point instructions for floating-point operations. When <samp class="option">-msoft-float</samp> is specified, functions in <samp class="file">libgcc.a</samp> are used to perform floating-point operations. Unless they are replaced by routines that emulate the floating-point operations, or compiled in such a way as to call such emulations routines, these routines issue floating-point operations. If you are compiling for an Alpha without floating-point operations, you must ensure that the library is built so as not to call them. </p> <p>Note that Alpha implementations without floating-point operations are required to have floating-point registers. </p> </dd> <dt>
 <span><code class="code">-mfp-reg</code><a class="copiable-link" href="#index-mfp-reg"> ¶</a></span>
</dt> <dt><code class="code">-mno-fp-regs</code></dt> <dd>
<p>Generate code that uses (does not use) the floating-point register set. <samp class="option">-mno-fp-regs</samp> implies <samp class="option">-msoft-float</samp>. If the floating-point register set is not used, floating-point operands are passed in integer registers as if they were integers and floating-point results are passed in <code class="code">$0</code> instead of <code class="code">$f0</code>. This is a non-standard calling sequence, so any function with a floating-point argument or return value called by code compiled with <samp class="option">-mno-fp-regs</samp> must also be compiled with that option. </p> <p>A typical use of this option is building a kernel that does not use, and hence need not save and restore, any floating-point registers. </p> </dd> <dt>
<span><code class="code">-mieee</code><a class="copiable-link" href="#index-mieee"> ¶</a></span>
</dt> <dd>
<p>The Alpha architecture implements floating-point hardware optimized for maximum performance. It is mostly compliant with the IEEE floating-point standard. However, for full compliance, software assistance is required. This option generates code fully IEEE-compliant code <em class="emph">except</em> that the <var class="var">inexact-flag</var> is not maintained (see below). If this option is turned on, the preprocessor macro <code class="code">_IEEE_FP</code> is defined during compilation. The resulting code is less efficient but is able to correctly support denormalized numbers and exceptional IEEE values such as not-a-number and plus/minus infinity. Other Alpha compilers call this option <samp class="option">-ieee_with_no_inexact</samp>. </p> </dd> <dt>
<span><code class="code">-mieee-with-inexact</code><a class="copiable-link" href="#index-mieee-with-inexact"> ¶</a></span>
</dt> <dd>
<p>This is like <samp class="option">-mieee</samp> except the generated code also maintains the IEEE <var class="var">inexact-flag</var>. Turning on this option causes the generated code to implement fully-compliant IEEE math. In addition to <code class="code">_IEEE_FP</code>, <code class="code">_IEEE_FP_EXACT</code> is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute significantly slower than the code generated by default. Since there is very little code that depends on the <var class="var">inexact-flag</var>, you should normally not specify this option. Other Alpha compilers call this option <samp class="option">-ieee_with_inexact</samp>. </p> </dd> <dt>
<span><code class="code">-mfp-trap-mode=<var class="var">trap-mode</var></code><a class="copiable-link" href="#index-mfp-trap-mode"> ¶</a></span>
</dt> <dd>
<p>This option controls what floating-point related traps are enabled. Other Alpha compilers call this option <samp class="option">-fptm <var class="var">trap-mode</var></samp>. The trap mode can be set to one of four values: </p> <dl class="table"> <dt>‘<samp class="samp">n</samp>’</dt> <dd>
<p>This is the default (normal) setting. The only traps that are enabled are the ones that cannot be disabled in software (e.g., division by zero trap). </p> </dd> <dt>‘<samp class="samp">u</samp>’</dt> <dd>
<p>In addition to the traps enabled by ‘<samp class="samp">n</samp>’, underflow traps are enabled as well. </p> </dd> <dt>‘<samp class="samp">su</samp>’</dt> <dd>
<p>Like ‘<samp class="samp">u</samp>’, but the instructions are marked to be safe for software completion (see Alpha architecture manual for details). </p> </dd> <dt>‘<samp class="samp">sui</samp>’</dt> <dd><p>Like ‘<samp class="samp">su</samp>’, but inexact traps are enabled as well. </p></dd> </dl> </dd> <dt>
<span><code class="code">-mfp-rounding-mode=<var class="var">rounding-mode</var></code><a class="copiable-link" href="#index-mfp-rounding-mode"> ¶</a></span>
</dt> <dd>
<p>Selects the IEEE rounding mode. Other Alpha compilers call this option <samp class="option">-fprm <var class="var">rounding-mode</var></samp>. The <var class="var">rounding-mode</var> can be one of: </p> <dl class="table"> <dt>‘<samp class="samp">n</samp>’</dt> <dd>
<p>Normal IEEE rounding mode. Floating-point numbers are rounded towards the nearest machine number or towards the even machine number in case of a tie. </p> </dd> <dt>‘<samp class="samp">m</samp>’</dt> <dd>
<p>Round towards minus infinity. </p> </dd> <dt>‘<samp class="samp">c</samp>’</dt> <dd>
<p>Chopped rounding mode. Floating-point numbers are rounded towards zero. </p> </dd> <dt>‘<samp class="samp">d</samp>’</dt> <dd><p>Dynamic rounding mode. A field in the floating-point control register (<var class="var">fpcr</var>, see Alpha architecture reference manual) controls the rounding mode in effect. The C library initializes this register for rounding towards plus infinity. Thus, unless your program modifies the <var class="var">fpcr</var>, ‘<samp class="samp">d</samp>’ corresponds to round towards plus infinity. </p></dd> </dl> </dd> <dt>
<span><code class="code">-mtrap-precision=<var class="var">trap-precision</var></code><a class="copiable-link" href="#index-mtrap-precision"> ¶</a></span>
</dt> <dd>
<p>In the Alpha architecture, floating-point traps are imprecise. This means without software assistance it is impossible to recover from a floating trap and program execution normally needs to be terminated. GCC can generate code that can assist operating system trap handlers in determining the exact location that caused a floating-point trap. Depending on the requirements of an application, different levels of precisions can be selected: </p> <dl class="table"> <dt>‘<samp class="samp">p</samp>’</dt> <dd>
<p>Program precision. This option is the default and means a trap handler can only identify which program caused a floating-point exception. </p> </dd> <dt>‘<samp class="samp">f</samp>’</dt> <dd>
<p>Function precision. The trap handler can determine the function that caused a floating-point exception. </p> </dd> <dt>‘<samp class="samp">i</samp>’</dt> <dd><p>Instruction precision. The trap handler can determine the exact instruction that caused a floating-point exception. </p></dd> </dl> <p>Other Alpha compilers provide the equivalent options called <samp class="option">-scope_safe</samp> and <samp class="option">-resumption_safe</samp>. </p> </dd> <dt>
<span><code class="code">-mieee-conformant</code><a class="copiable-link" href="#index-mieee-conformant"> ¶</a></span>
</dt> <dd>
<p>This option marks the generated code as IEEE conformant. You must not use this option unless you also specify <samp class="option">-mtrap-precision=i</samp> and either <samp class="option">-mfp-trap-mode=su</samp> or <samp class="option">-mfp-trap-mode=sui</samp>. Its only effect is to emit the line ‘<samp class="samp">.eflag 48</samp>’ in the function prologue of the generated assembly file. </p> </dd> <dt>
<span><code class="code">-mbuild-constants</code><a class="copiable-link" href="#index-mbuild-constants"> ¶</a></span>
</dt> <dd>
<p>Normally GCC examines a 32- or 64-bit integer constant to see if it can construct it from smaller constants in two or three instructions. If it cannot, it outputs the constant as a literal and generates code to load it from the data segment at run time. </p> <p>Use this option to require GCC to construct <em class="emph">all</em> integer constants using code, even if it takes more instructions (the maximum is six). </p> <p>You typically use this option to build a shared library dynamic loader. Itself a shared library, it must relocate itself in memory before it can find the variables and constants in its own data segment. </p> </dd> <dt>
       <span><code class="code">-mbwx</code><a class="copiable-link" href="#index-mbwx"> ¶</a></span>
</dt> <dt><code class="code">-mno-bwx</code></dt> <dt><code class="code">-mcix</code></dt> <dt><code class="code">-mno-cix</code></dt> <dt><code class="code">-mfix</code></dt> <dt><code class="code">-mno-fix</code></dt> <dt><code class="code">-mmax</code></dt> <dt><code class="code">-mno-max</code></dt> <dd>
<p>Indicate whether GCC should generate code to use the optional BWX, CIX, FIX and MAX instruction sets. The default is to use the instruction sets supported by the CPU type specified via <samp class="option">-mcpu=</samp> option or that of the CPU on which GCC was built if none is specified. </p> </dd> <dt>
 <span><code class="code">-mfloat-vax</code><a class="copiable-link" href="#index-mfloat-vax"> ¶</a></span>
</dt> <dt><code class="code">-mfloat-ieee</code></dt> <dd>
<p>Generate code that uses (does not use) VAX F and G floating-point arithmetic instead of IEEE single and double precision. </p> </dd> <dt>
 <span><code class="code">-mexplicit-relocs</code><a class="copiable-link" href="#index-mexplicit-relocs"> ¶</a></span>
</dt> <dt><code class="code">-mno-explicit-relocs</code></dt> <dd>
<p>Older Alpha assemblers provided no way to generate symbol relocations except via assembler macros. Use of these macros does not allow optimal instruction scheduling. GNU binutils as of version 2.12 supports a new syntax that allows the compiler to explicitly mark which relocations should apply to which instructions. This option is mostly useful for debugging, as GCC detects the capabilities of the assembler when it is built and sets the default accordingly. </p> </dd> <dt>
 <span><code class="code">-msmall-data</code><a class="copiable-link" href="#index-msmall-data"> ¶</a></span>
</dt> <dt><code class="code">-mlarge-data</code></dt> <dd>
<p>When <samp class="option">-mexplicit-relocs</samp> is in effect, static data is accessed via <em class="dfn">gp-relative</em> relocations. When <samp class="option">-msmall-data</samp> is used, objects 8 bytes long or smaller are placed in a <em class="dfn">small data area</em> (the <code class="code">.sdata</code> and <code class="code">.sbss</code> sections) and are accessed via 16-bit relocations off of the <code class="code">$gp</code> register. This limits the size of the small data area to 64KB, but allows the variables to be directly accessed via a single instruction. </p> <p>The default is <samp class="option">-mlarge-data</samp>. With this option the data area is limited to just below 2GB. Programs that require more than 2GB of data must use <code class="code">malloc</code> or <code class="code">mmap</code> to allocate the data in the heap instead of in the program’s data segment. </p> <p>When generating code for shared libraries, <samp class="option">-fpic</samp> implies <samp class="option">-msmall-data</samp> and <samp class="option">-fPIC</samp> implies <samp class="option">-mlarge-data</samp>. </p> </dd> <dt>
 <span><code class="code">-msmall-text</code><a class="copiable-link" href="#index-msmall-text"> ¶</a></span>
</dt> <dt><code class="code">-mlarge-text</code></dt> <dd>
<p>When <samp class="option">-msmall-text</samp> is used, the compiler assumes that the code of the entire program (or shared library) fits in 4MB, and is thus reachable with a branch instruction. When <samp class="option">-msmall-data</samp> is used, the compiler can assume that all local symbols share the same <code class="code">$gp</code> value, and thus reduce the number of instructions required for a function call from 4 to 1. </p> <p>The default is <samp class="option">-mlarge-text</samp>. </p> </dd> <dt>
<span><code class="code">-mcpu=<var class="var">cpu_type</var></code><a class="copiable-link" href="#index-mcpu-4"> ¶</a></span>
</dt> <dd>
<p>Set the instruction set and instruction scheduling parameters for machine type <var class="var">cpu_type</var>. You can specify either the ‘<samp class="samp">EV</samp>’ style name or the corresponding chip number. GCC supports scheduling parameters for the EV4, EV5 and EV6 family of processors and chooses the default values for the instruction set from the processor you specify. If you do not specify a processor type, GCC defaults to the processor on which the compiler was built. </p> <p>Supported values for <var class="var">cpu_type</var> are </p> <dl class="table"> <dt>‘<samp class="samp">ev4</samp>’</dt> <dt>‘<samp class="samp">ev45</samp>’</dt> <dt>‘<samp class="samp">21064</samp>’</dt> <dd>
<p>Schedules as an EV4 and has no instruction set extensions. </p> </dd> <dt>‘<samp class="samp">ev5</samp>’</dt> <dt>‘<samp class="samp">21164</samp>’</dt> <dd>
<p>Schedules as an EV5 and has no instruction set extensions. </p> </dd> <dt>‘<samp class="samp">ev56</samp>’</dt> <dt>‘<samp class="samp">21164a</samp>’</dt> <dd>
<p>Schedules as an EV5 and supports the BWX extension. </p> </dd> <dt>‘<samp class="samp">pca56</samp>’</dt> <dt>‘<samp class="samp">21164pc</samp>’</dt> <dt>‘<samp class="samp">21164PC</samp>’</dt> <dd>
<p>Schedules as an EV5 and supports the BWX and MAX extensions. </p> </dd> <dt>‘<samp class="samp">ev6</samp>’</dt> <dt>‘<samp class="samp">21264</samp>’</dt> <dd>
<p>Schedules as an EV6 and supports the BWX, FIX, and MAX extensions. </p> </dd> <dt>‘<samp class="samp">ev67</samp>’</dt> <dt>‘<samp class="samp">21264a</samp>’</dt> <dd><p>Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions. </p></dd> </dl> <p>Native toolchains also support the value ‘<samp class="samp">native</samp>’, which selects the best architecture option for the host processor. <samp class="option">-mcpu=native</samp> has no effect if GCC does not recognize the processor. </p> </dd> <dt>
<span><code class="code">-mtune=<var class="var">cpu_type</var></code><a class="copiable-link" href="#index-mtune-6"> ¶</a></span>
</dt> <dd>
<p>Set only the instruction scheduling parameters for machine type <var class="var">cpu_type</var>. The instruction set is not changed. </p> <p>Native toolchains also support the value ‘<samp class="samp">native</samp>’, which selects the best architecture option for the host processor. <samp class="option">-mtune=native</samp> has no effect if GCC does not recognize the processor. </p> </dd> <dt>
<span><code class="code">-mmemory-latency=<var class="var">time</var></code><a class="copiable-link" href="#index-mmemory-latency"> ¶</a></span>
</dt> <dd>
<p>Sets the latency the scheduler should assume for typical memory references as seen by the application. This number is highly dependent on the memory access patterns used by the application and the size of the external cache on the machine. </p> <p>Valid options for <var class="var">time</var> are </p> <dl class="table"> <dt>‘<samp class="samp"><var class="var">number</var></samp>’</dt> <dd>
<p>A decimal number representing clock cycles. </p> </dd> <dt>‘<samp class="samp">L1</samp>’</dt> <dt>‘<samp class="samp">L2</samp>’</dt> <dt>‘<samp class="samp">L3</samp>’</dt> <dt>‘<samp class="samp">main</samp>’</dt> <dd>
<p>The compiler contains estimates of the number of clock cycles for “typical” EV4 &amp; EV5 hardware for the Level 1, 2 &amp; 3 caches (also called Dcache, Scache, and Bcache), as well as to main memory. Note that L3 is only valid for EV5. </p> </dd> </dl> </dd> </dl> </div>  <div class="nav-panel"> <p> Next: <a href="ebpf-options">eBPF Options</a>, Previous: <a href="darwin-options">Darwin Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
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