devdocs/gcc~13/mips-paired-single-support.html


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<div class="subsection-level-extent" id="MIPS-Paired-Single-Support"> <div class="nav-panel"> <p> Next: <a href="mips-loongson-built-in-functions" accesskey="n" rel="next">MIPS Loongson Built-in Functions</a>, Previous: <a href="mips-dsp-built-in-functions" accesskey="p" rel="prev">MIPS DSP Built-in Functions</a>, Up: <a href="target-builtins" accesskey="u" rel="up">Built-in Functions Specific to Particular Target Machines</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="MIPS-Paired-Single-Support-1"><span>6.60.16 MIPS Paired-Single Support<a class="copiable-link" href="#MIPS-Paired-Single-Support-1"> ¶</a></span></h1> <p>The MIPS64 architecture includes a number of instructions that operate on pairs of single-precision floating-point values. Each pair is packed into a 64-bit floating-point register, with one element being designated the “upper half” and the other being designated the “lower half”. </p> <p>GCC supports paired-single operations using both the generic vector extensions (see <a class="pxref" href="vector-extensions">Using Vector Instructions through Built-in Functions</a>) and a collection of MIPS-specific built-in functions. Both kinds of support are enabled by the <samp class="option">-mpaired-single</samp> command-line option. </p> <p>The vector type associated with paired-single values is usually called <code class="code">v2sf</code>. It can be defined in C as follows: </p> <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">typedef float v2sf __attribute__ ((vector_size (8)));</pre>
</div> <p><code class="code">v2sf</code> values are initialized in the same way as aggregates. For example: </p> <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">v2sf a = {1.5, 9.1};
v2sf b;
float e, f;
b = (v2sf) {e, f};</pre>
</div> <p><em class="emph">Note:</em> The CPU’s endianness determines which value is stored in the upper half of a register and which value is stored in the lower half. On little-endian targets, the first value is the lower one and the second value is the upper one. The opposite order applies to big-endian targets. For example, the code above sets the lower half of <code class="code">a</code> to <code class="code">1.5</code> on little-endian targets and <code class="code">9.1</code> on big-endian targets. </p> </div><div class="_attribution">
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