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+<div class="subsection-level-extent" id="ARC-Options"> <div class="nav-panel"> <p> Next: <a href="arm-options" accesskey="n" rel="next">ARM Options</a>, Previous: <a href="amd-gcn-options" accesskey="p" rel="prev">AMD GCN Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="ARC-Options-1"><span>3.19.4 ARC Options<a class="copiable-link" href="#ARC-Options-1"> ¶</a></span></h1>  <p>The following options control the architecture variant for which code is being compiled: </p> <dl class="table"> <dt>
+<span><code class="code">-mbarrel-shifter</code><a class="copiable-link" href="#index-mbarrel-shifter"> ¶</a></span>
+</dt> <dd>
+<p>Generate instructions supported by barrel shifter. This is the default unless <samp class="option">-mcpu=ARC601</samp> or ‘<samp class="samp">-mcpu=ARCEM</samp>’ is in effect. </p> </dd> <dt>
+<span><code class="code">-mjli-always</code><a class="copiable-link" href="#index-mjli-always"> ¶</a></span>
+</dt> <dd>
+<p>Force to call a function using jli_s instruction. This option is valid only for ARCv2 architecture. </p> </dd> <dt>
+<span><code class="code">-mcpu=<var class="var">cpu</var></code><a class="copiable-link" href="#index-mcpu-1"> ¶</a></span>
+</dt> <dd>
+<p>Set architecture type, register usage, and instruction scheduling parameters for <var class="var">cpu</var>. There are also shortcut alias options available for backward compatibility and convenience. Supported values for <var class="var">cpu</var> are </p> <dl class="table"> <dt>
+ <span>‘<samp class="samp">arc600</samp>’<a class="copiable-link" href="#index-mA6"> ¶</a></span>
+</dt> <dd>
+<p>Compile for ARC600. Aliases: <samp class="option">-mA6</samp>, <samp class="option">-mARC600</samp>. </p> </dd> <dt>
+<span>‘<samp class="samp">arc601</samp>’<a class="copiable-link" href="#index-mARC601"> ¶</a></span>
+</dt> <dd>
+<p>Compile for ARC601. Alias: <samp class="option">-mARC601</samp>. </p> </dd> <dt>
+ <span>‘<samp class="samp">arc700</samp>’<a class="copiable-link" href="#index-mA7"> ¶</a></span>
+</dt> <dd>
+<p>Compile for ARC700. Aliases: <samp class="option">-mA7</samp>, <samp class="option">-mARC700</samp>. This is the default when configured with <samp class="option">--with-cpu=arc700</samp>. </p> </dd> <dt>‘<samp class="samp">arcem</samp>’</dt> <dd>
+<p>Compile for ARC EM. </p> </dd> <dt>‘<samp class="samp">archs</samp>’</dt> <dd>
+<p>Compile for ARC HS. </p> </dd> <dt>‘<samp class="samp">em</samp>’</dt> <dd>
+<p>Compile for ARC EM CPU with no hardware extensions. </p> </dd> <dt>‘<samp class="samp">em4</samp>’</dt> <dd>
+<p>Compile for ARC EM4 CPU. </p> </dd> <dt>‘<samp class="samp">em4_dmips</samp>’</dt> <dd>
+<p>Compile for ARC EM4 DMIPS CPU. </p> </dd> <dt>‘<samp class="samp">em4_fpus</samp>’</dt> <dd>
+<p>Compile for ARC EM4 DMIPS CPU with the single-precision floating-point extension. </p> </dd> <dt>‘<samp class="samp">em4_fpuda</samp>’</dt> <dd>
+<p>Compile for ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions. </p> </dd> <dt>‘<samp class="samp">hs</samp>’</dt> <dd>
+<p>Compile for ARC HS CPU with no hardware extensions except the atomic instructions. </p> </dd> <dt>‘<samp class="samp">hs34</samp>’</dt> <dd>
+<p>Compile for ARC HS34 CPU. </p> </dd> <dt>‘<samp class="samp">hs38</samp>’</dt> <dd>
+<p>Compile for ARC HS38 CPU. </p> </dd> <dt>‘<samp class="samp">hs38_linux</samp>’</dt> <dd>
+<p>Compile for ARC HS38 CPU with all hardware extensions on. </p> </dd> <dt>‘<samp class="samp">hs4x</samp>’</dt> <dd>
+<p>Compile for ARC HS4x CPU. </p> </dd> <dt>‘<samp class="samp">hs4xd</samp>’</dt> <dd>
+<p>Compile for ARC HS4xD CPU. </p> </dd> <dt>‘<samp class="samp">hs4x_rel31</samp>’</dt> <dd>
+<p>Compile for ARC HS4x CPU release 3.10a. </p> </dd> <dt>‘<samp class="samp">arc600_norm</samp>’</dt> <dd>
+<p>Compile for ARC 600 CPU with <code class="code">norm</code> instructions enabled. </p> </dd> <dt>‘<samp class="samp">arc600_mul32x16</samp>’</dt> <dd>
+<p>Compile for ARC 600 CPU with <code class="code">norm</code> and 32x16-bit multiply instructions enabled. </p> </dd> <dt>‘<samp class="samp">arc600_mul64</samp>’</dt> <dd>
+<p>Compile for ARC 600 CPU with <code class="code">norm</code> and <code class="code">mul64</code>-family instructions enabled. </p> </dd> <dt>‘<samp class="samp">arc601_norm</samp>’</dt> <dd>
+<p>Compile for ARC 601 CPU with <code class="code">norm</code> instructions enabled. </p> </dd> <dt>‘<samp class="samp">arc601_mul32x16</samp>’</dt> <dd>
+<p>Compile for ARC 601 CPU with <code class="code">norm</code> and 32x16-bit multiply instructions enabled. </p> </dd> <dt>‘<samp class="samp">arc601_mul64</samp>’</dt> <dd>
+<p>Compile for ARC 601 CPU with <code class="code">norm</code> and <code class="code">mul64</code>-family instructions enabled. </p> </dd> <dt>‘<samp class="samp">nps400</samp>’</dt> <dd>
+<p>Compile for ARC 700 on NPS400 chip. </p> </dd> <dt>‘<samp class="samp">em_mini</samp>’</dt> <dd>
+<p>Compile for ARC EM minimalist configuration featuring reduced register set. </p> </dd> </dl> </dd> <dt>
+ <span><code class="code">-mdpfp</code><a class="copiable-link" href="#index-mdpfp"> ¶</a></span>
+</dt> <dt><code class="code">-mdpfp-compact</code></dt> <dd>
+<p>Generate double-precision FPX instructions, tuned for the compact implementation. </p> </dd> <dt>
+<span><code class="code">-mdpfp-fast</code><a class="copiable-link" href="#index-mdpfp-fast"> ¶</a></span>
+</dt> <dd>
+<p>Generate double-precision FPX instructions, tuned for the fast implementation. </p> </dd> <dt>
+<span><code class="code">-mno-dpfp-lrsr</code><a class="copiable-link" href="#index-mno-dpfp-lrsr"> ¶</a></span>
+</dt> <dd>
+<p>Disable <code class="code">lr</code> and <code class="code">sr</code> instructions from using FPX extension aux registers. </p> </dd> <dt>
+<span><code class="code">-mea</code><a class="copiable-link" href="#index-mea"> ¶</a></span>
+</dt> <dd>
+<p>Generate extended arithmetic instructions. Currently only <code class="code">divaw</code>, <code class="code">adds</code>, <code class="code">subs</code>, and <code class="code">sat16</code> are supported. Only valid for <samp class="option">-mcpu=ARC700</samp>. </p> </dd> <dt>
+ <span><code class="code">-mno-mpy</code><a class="copiable-link" href="#index-mno-mpy"> ¶</a></span>
+</dt> <dd>
+<p>Do not generate <code class="code">mpy</code>-family instructions for ARC700. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mmul32x16</code><a class="copiable-link" href="#index-mmul32x16"> ¶</a></span>
+</dt> <dd>
+<p>Generate 32x16-bit multiply and multiply-accumulate instructions. </p> </dd> <dt>
+<span><code class="code">-mmul64</code><a class="copiable-link" href="#index-mmul64"> ¶</a></span>
+</dt> <dd>
+<p>Generate <code class="code">mul64</code> and <code class="code">mulu64</code> instructions. Only valid for <samp class="option">-mcpu=ARC600</samp>. </p> </dd> <dt>
+<span><code class="code">-mnorm</code><a class="copiable-link" href="#index-mnorm"> ¶</a></span>
+</dt> <dd>
+<p>Generate <code class="code">norm</code> instructions. This is the default if <samp class="option">-mcpu=ARC700</samp> is in effect. </p> </dd> <dt>
+ <span><code class="code">-mspfp</code><a class="copiable-link" href="#index-mspfp"> ¶</a></span>
+</dt> <dt><code class="code">-mspfp-compact</code></dt> <dd>
+<p>Generate single-precision FPX instructions, tuned for the compact implementation. </p> </dd> <dt>
+<span><code class="code">-mspfp-fast</code><a class="copiable-link" href="#index-mspfp-fast"> ¶</a></span>
+</dt> <dd>
+<p>Generate single-precision FPX instructions, tuned for the fast implementation. </p> </dd> <dt>
+<span><code class="code">-msimd</code><a class="copiable-link" href="#index-msimd"> ¶</a></span>
+</dt> <dd>
+<p>Enable generation of ARC SIMD instructions via target-specific builtins. Only valid for <samp class="option">-mcpu=ARC700</samp>. </p> </dd> <dt>
+<span><code class="code">-msoft-float</code><a class="copiable-link" href="#index-msoft-float"> ¶</a></span>
+</dt> <dd>
+<p>This option ignored; it is provided for compatibility purposes only. Software floating-point code is emitted by default, and this default can overridden by FPX options; <samp class="option">-mspfp</samp>, <samp class="option">-mspfp-compact</samp>, or <samp class="option">-mspfp-fast</samp> for single precision, and <samp class="option">-mdpfp</samp>, <samp class="option">-mdpfp-compact</samp>, or <samp class="option">-mdpfp-fast</samp> for double precision. </p> </dd> <dt>
+<span><code class="code">-mswap</code><a class="copiable-link" href="#index-mswap"> ¶</a></span>
+</dt> <dd>
+<p>Generate <code class="code">swap</code> instructions. </p> </dd> <dt>
+<span><code class="code">-matomic</code><a class="copiable-link" href="#index-matomic"> ¶</a></span>
+</dt> <dd>
+<p>This enables use of the locked load/store conditional extension to implement atomic memory built-in functions. Not available for ARC 6xx or ARC EM cores. </p> </dd> <dt>
+<span><code class="code">-mdiv-rem</code><a class="copiable-link" href="#index-mdiv-rem"> ¶</a></span>
+</dt> <dd>
+<p>Enable <code class="code">div</code> and <code class="code">rem</code> instructions for ARCv2 cores. </p> </dd> <dt>
+<span><code class="code">-mcode-density</code><a class="copiable-link" href="#index-mcode-density"> ¶</a></span>
+</dt> <dd>
+<p>Enable code density instructions for ARC EM. This option is on by default for ARC HS. </p> </dd> <dt>
+<span><code class="code">-mll64</code><a class="copiable-link" href="#index-mll64"> ¶</a></span>
+</dt> <dd>
+<p>Enable double load/store operations for ARC HS cores. </p> </dd> <dt>
+<span><code class="code">-mtp-regno=<var class="var">regno</var></code><a class="copiable-link" href="#index-mtp-regno"> ¶</a></span>
+</dt> <dd>
+<p>Specify thread pointer register number. </p> </dd> <dt>
+<span><code class="code">-mmpy-option=<var class="var">multo</var></code><a class="copiable-link" href="#index-mmpy-option"> ¶</a></span>
+</dt> <dd>
+<p>Compile ARCv2 code with a multiplier design option. You can specify the option using either a string or numeric value for <var class="var">multo</var>. ‘<samp class="samp">wlh1</samp>’ is the default value. The recognized values are: </p> <dl class="table"> <dt>‘<samp class="samp">0</samp>’</dt> <dt>‘<samp class="samp">none</samp>’</dt> <dd>
+<p>No multiplier available. </p> </dd> <dt>‘<samp class="samp">1</samp>’</dt> <dt>‘<samp class="samp">w</samp>’</dt> <dd>
+<p>16x16 multiplier, fully pipelined. The following instructions are enabled: <code class="code">mpyw</code> and <code class="code">mpyuw</code>. </p> </dd> <dt>‘<samp class="samp">2</samp>’</dt> <dt>‘<samp class="samp">wlh1</samp>’</dt> <dd>
+<p>32x32 multiplier, fully pipelined (1 stage). The following instructions are additionally enabled: <code class="code">mpy</code>, <code class="code">mpyu</code>, <code class="code">mpym</code>, <code class="code">mpymu</code>, and <code class="code">mpy_s</code>. </p> </dd> <dt>‘<samp class="samp">3</samp>’</dt> <dt>‘<samp class="samp">wlh2</samp>’</dt> <dd>
+<p>32x32 multiplier, fully pipelined (2 stages). The following instructions are additionally enabled: <code class="code">mpy</code>, <code class="code">mpyu</code>, <code class="code">mpym</code>, <code class="code">mpymu</code>, and <code class="code">mpy_s</code>. </p> </dd> <dt>‘<samp class="samp">4</samp>’</dt> <dt>‘<samp class="samp">wlh3</samp>’</dt> <dd>
+<p>Two 16x16 multipliers, blocking, sequential. The following instructions are additionally enabled: <code class="code">mpy</code>, <code class="code">mpyu</code>, <code class="code">mpym</code>, <code class="code">mpymu</code>, and <code class="code">mpy_s</code>. </p> </dd> <dt>‘<samp class="samp">5</samp>’</dt> <dt>‘<samp class="samp">wlh4</samp>’</dt> <dd>
+<p>One 16x16 multiplier, blocking, sequential. The following instructions are additionally enabled: <code class="code">mpy</code>, <code class="code">mpyu</code>, <code class="code">mpym</code>, <code class="code">mpymu</code>, and <code class="code">mpy_s</code>. </p> </dd> <dt>‘<samp class="samp">6</samp>’</dt> <dt>‘<samp class="samp">wlh5</samp>’</dt> <dd>
+<p>One 32x4 multiplier, blocking, sequential. The following instructions are additionally enabled: <code class="code">mpy</code>, <code class="code">mpyu</code>, <code class="code">mpym</code>, <code class="code">mpymu</code>, and <code class="code">mpy_s</code>. </p> </dd> <dt>‘<samp class="samp">7</samp>’</dt> <dt>‘<samp class="samp">plus_dmpy</samp>’</dt> <dd>
+<p>ARC HS SIMD support. </p> </dd> <dt>‘<samp class="samp">8</samp>’</dt> <dt>‘<samp class="samp">plus_macd</samp>’</dt> <dd>
+<p>ARC HS SIMD support. </p> </dd> <dt>‘<samp class="samp">9</samp>’</dt> <dt>‘<samp class="samp">plus_qmacw</samp>’</dt> <dd>
+<p>ARC HS SIMD support. </p> </dd> </dl> <p>This option is only available for ARCv2 cores. </p> </dd> <dt>
+<span><code class="code">-mfpu=<var class="var">fpu</var></code><a class="copiable-link" href="#index-mfpu"> ¶</a></span>
+</dt> <dd>
+<p>Enables support for specific floating-point hardware extensions for ARCv2 cores. Supported values for <var class="var">fpu</var> are: </p> <dl class="table"> <dt>‘<samp class="samp">fpus</samp>’</dt> <dd>
+<p>Enables support for single-precision floating-point hardware extensions. </p> </dd> <dt>‘<samp class="samp">fpud</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point hardware extensions. The single-precision floating-point extension is also enabled. Not available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpuda</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. The single-precision floating-point extension is also enabled. This option is only available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpuda_div</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. The single-precision floating-point, square-root, and divide extensions are also enabled. This option is only available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpuda_fma</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. The single-precision floating-point and fused multiply and add hardware extensions are also enabled. This option is only available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpuda_all</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point hardware extensions using double-precision assist instructions. All single-precision floating-point hardware extensions are also enabled. This option is only available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpus_div</samp>’</dt> <dd>
+<p>Enables support for single-precision floating-point, square-root and divide hardware extensions. </p> </dd> <dt>‘<samp class="samp">fpud_div</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point, square-root and divide hardware extensions. This option includes option ‘<samp class="samp">fpus_div</samp>’. Not available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpus_fma</samp>’</dt> <dd>
+<p>Enables support for single-precision floating-point and fused multiply and add hardware extensions. </p> </dd> <dt>‘<samp class="samp">fpud_fma</samp>’</dt> <dd>
+<p>Enables support for double-precision floating-point and fused multiply and add hardware extensions. This option includes option ‘<samp class="samp">fpus_fma</samp>’. Not available for ARC EM. </p> </dd> <dt>‘<samp class="samp">fpus_all</samp>’</dt> <dd>
+<p>Enables support for all single-precision floating-point hardware extensions. </p> </dd> <dt>‘<samp class="samp">fpud_all</samp>’</dt> <dd>
+<p>Enables support for all single- and double-precision floating-point hardware extensions. Not available for ARC EM. </p> </dd> </dl> </dd> <dt>
+<span><code class="code">-mirq-ctrl-saved=<var class="var">register-range</var>, <var class="var">blink</var>, <var class="var">lp_count</var></code><a class="copiable-link" href="#index-mirq-ctrl-saved"> ¶</a></span>
+</dt> <dd>
+<p>Specifies general-purposes registers that the processor automatically saves/restores on interrupt entry and exit. <var class="var">register-range</var> is specified as two registers separated by a dash. The register range always starts with <code class="code">r0</code>, the upper limit is <code class="code">fp</code> register. <var class="var">blink</var> and <var class="var">lp_count</var> are optional. This option is only valid for ARC EM and ARC HS cores. </p> </dd> <dt>
+<span><code class="code">-mrgf-banked-regs=<var class="var">number</var></code><a class="copiable-link" href="#index-mrgf-banked-regs"> ¶</a></span>
+</dt> <dd>
+<p>Specifies the number of registers replicated in second register bank on entry to fast interrupt. Fast interrupts are interrupts with the highest priority level P0. These interrupts save only PC and STATUS32 registers to avoid memory transactions during interrupt entry and exit sequences. Use this option when you are using fast interrupts in an ARC V2 family processor. Permitted values are 4, 8, 16, and 32. </p> </dd> <dt>
+<span><code class="code">-mlpc-width=<var class="var">width</var></code><a class="copiable-link" href="#index-mlpc-width"> ¶</a></span>
+</dt> <dd>
+<p>Specify the width of the <code class="code">lp_count</code> register. Valid values for <var class="var">width</var> are 8, 16, 20, 24, 28 and 32 bits. The default width is fixed to 32 bits. If the width is less than 32, the compiler does not attempt to transform loops in your program to use the zero-delay loop mechanism unless it is known that the <code class="code">lp_count</code> register can hold the required loop-counter value. Depending on the width specified, the compiler and run-time library might continue to use the loop mechanism for various needs. This option defines macro <code class="code">__ARC_LPC_WIDTH__</code> with the value of <var class="var">width</var>. </p> </dd> <dt>
+<span><code class="code">-mrf16</code><a class="copiable-link" href="#index-mrf16"> ¶</a></span>
+</dt> <dd>
+<p>This option instructs the compiler to generate code for a 16-entry register file. This option defines the <code class="code">__ARC_RF16__</code> preprocessor macro. </p> </dd> <dt>
+<span><code class="code">-mbranch-index</code><a class="copiable-link" href="#index-mbranch-index"> ¶</a></span>
+</dt> <dd>
+<p>Enable use of <code class="code">bi</code> or <code class="code">bih</code> instructions to implement jump tables. </p> </dd> </dl> <p>The following options are passed through to the assembler, and also define preprocessor macro symbols. </p> <dl class="table"> <dt>
+<span><code class="code">-mdsp-packa</code><a class="copiable-link" href="#index-mdsp-packa"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable the DSP Pack A extensions. Also sets the preprocessor symbol <code class="code">__Xdsp_packa</code>. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mdvbf</code><a class="copiable-link" href="#index-mdvbf"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable the dual Viterbi butterfly extension. Also sets the preprocessor symbol <code class="code">__Xdvbf</code>. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mlock</code><a class="copiable-link" href="#index-mlock"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable the locked load/store conditional extension. Also sets the preprocessor symbol <code class="code">__Xlock</code>. </p> </dd> <dt>
+<span><code class="code">-mmac-d16</code><a class="copiable-link" href="#index-mmac-d16"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler. Also sets the preprocessor symbol <code class="code">__Xxmac_d16</code>. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mmac-24</code><a class="copiable-link" href="#index-mmac-24"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler. Also sets the preprocessor symbol <code class="code">__Xxmac_24</code>. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mrtsc</code><a class="copiable-link" href="#index-mrtsc"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable the 64-bit time-stamp counter extension instruction. Also sets the preprocessor symbol <code class="code">__Xrtsc</code>. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mswape</code><a class="copiable-link" href="#index-mswape"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable the swap byte ordering extension instruction. Also sets the preprocessor symbol <code class="code">__Xswape</code>. </p> </dd> <dt>
+<span><code class="code">-mtelephony</code><a class="copiable-link" href="#index-mtelephony"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable dual- and single-operand instructions for telephony. Also sets the preprocessor symbol <code class="code">__Xtelephony</code>. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mxy</code><a class="copiable-link" href="#index-mxy"> ¶</a></span>
+</dt> <dd>
+<p>Passed down to the assembler to enable the XY memory extension. Also sets the preprocessor symbol <code class="code">__Xxy</code>. </p> </dd> </dl> <p>The following options control how the assembly code is annotated: </p> <dl class="table"> <dt>
+<span><code class="code">-misize</code><a class="copiable-link" href="#index-misize"> ¶</a></span>
+</dt> <dd>
+<p>Annotate assembler instructions with estimated addresses. </p> </dd> <dt>
+<span><code class="code">-mannotate-align</code><a class="copiable-link" href="#index-mannotate-align"> ¶</a></span>
+</dt> <dd>
+<p>Explain what alignment considerations lead to the decision to make an instruction short or long. </p> </dd> </dl> <p>The following options are passed through to the linker: </p> <dl class="table"> <dt>
+<span><code class="code">-marclinux</code><a class="copiable-link" href="#index-marclinux"> ¶</a></span>
+</dt> <dd>
+<p>Passed through to the linker, to specify use of the <code class="code">arclinux</code> emulation. This option is enabled by default in tool chains built for <code class="code">arc-linux-uclibc</code> and <code class="code">arceb-linux-uclibc</code> targets when profiling is not requested. </p> </dd> <dt>
+<span><code class="code">-marclinux_prof</code><a class="copiable-link" href="#index-marclinux_005fprof"> ¶</a></span>
+</dt> <dd>
+<p>Passed through to the linker, to specify use of the <code class="code">arclinux_prof</code> emulation. This option is enabled by default in tool chains built for <code class="code">arc-linux-uclibc</code> and <code class="code">arceb-linux-uclibc</code> targets when profiling is requested. </p> </dd> </dl> <p>The following options control the semantics of generated code: </p> <dl class="table"> <dt>
+<span><code class="code">-mlong-calls</code><a class="copiable-link" href="#index-mlong-calls-1"> ¶</a></span>
+</dt> <dd>
+<p>Generate calls as register indirect calls, thus providing access to the full 32-bit address range. </p> </dd> <dt>
+<span><code class="code">-mmedium-calls</code><a class="copiable-link" href="#index-mmedium-calls"> ¶</a></span>
+</dt> <dd>
+<p>Don’t use less than 25-bit addressing range for calls, which is the offset available for an unconditional branch-and-link instruction. Conditional execution of function calls is suppressed, to allow use of the 25-bit range, rather than the 21-bit range with conditional branch-and-link. This is the default for tool chains built for <code class="code">arc-linux-uclibc</code> and <code class="code">arceb-linux-uclibc</code> targets. </p> </dd> <dt>
+<span><code class="code">-G <var class="var">num</var></code><a class="copiable-link" href="#index-G"> ¶</a></span>
+</dt> <dd>
+<p>Put definitions of externally-visible data in a small data section if that data is no bigger than <var class="var">num</var> bytes. The default value of <var class="var">num</var> is 4 for any ARC configuration, or 8 when we have double load/store operations. </p> </dd> <dt>
+ <span><code class="code">-mno-sdata</code><a class="copiable-link" href="#index-mno-sdata"> ¶</a></span>
+</dt> <dd>
+<p>Do not generate sdata references. This is the default for tool chains built for <code class="code">arc-linux-uclibc</code> and <code class="code">arceb-linux-uclibc</code> targets. </p> </dd> <dt>
+<span><code class="code">-mvolatile-cache</code><a class="copiable-link" href="#index-mvolatile-cache"> ¶</a></span>
+</dt> <dd>
+<p>Use ordinarily cached memory accesses for volatile references. This is the default. </p> </dd> <dt>
+ <span><code class="code">-mno-volatile-cache</code><a class="copiable-link" href="#index-mno-volatile-cache"> ¶</a></span>
+</dt> <dd>
+<p>Enable cache bypass for volatile references. </p> </dd> </dl> <p>The following options fine tune code generation: </p>
+<dl class="table"> <dt>
+<span><code class="code">-malign-call</code><a class="copiable-link" href="#index-malign-call"> ¶</a></span>
+</dt> <dd>
+<p>Does nothing. Preserved for backward compatibility. </p> </dd> <dt>
+<span><code class="code">-mauto-modify-reg</code><a class="copiable-link" href="#index-mauto-modify-reg"> ¶</a></span>
+</dt> <dd>
+<p>Enable the use of pre/post modify with register displacement. </p> </dd> <dt>
+<span><code class="code">-mbbit-peephole</code><a class="copiable-link" href="#index-mbbit-peephole"> ¶</a></span>
+</dt> <dd>
+<p>Enable bbit peephole2. </p> </dd> <dt>
+<span><code class="code">-mno-brcc</code><a class="copiable-link" href="#index-mno-brcc"> ¶</a></span>
+</dt> <dd>
+<p>This option disables a target-specific pass in <samp class="file">arc_reorg</samp> to generate compare-and-branch (<code class="code">br<var class="var">cc</var></code>) instructions. It has no effect on generation of these instructions driven by the combiner pass. </p> </dd> <dt>
+<span><code class="code">-mcase-vector-pcrel</code><a class="copiable-link" href="#index-mcase-vector-pcrel"> ¶</a></span>
+</dt> <dd>
+<p>Use PC-relative switch case tables to enable case table shortening. This is the default for <samp class="option">-Os</samp>. </p> </dd> <dt>
+<span><code class="code">-mcompact-casesi</code><a class="copiable-link" href="#index-mcompact-casesi"> ¶</a></span>
+</dt> <dd>
+<p>Enable compact <code class="code">casesi</code> pattern. This is the default for <samp class="option">-Os</samp>, and only available for ARCv1 cores. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mno-cond-exec</code><a class="copiable-link" href="#index-mno-cond-exec"> ¶</a></span>
+</dt> <dd>
+<p>Disable the ARCompact-specific pass to generate conditional execution instructions. </p> <p>Due to delay slot scheduling and interactions between operand numbers, literal sizes, instruction lengths, and the support for conditional execution, the target-independent pass to generate conditional execution is often lacking, so the ARC port has kept a special pass around that tries to find more conditional execution generation opportunities after register allocation, branch shortening, and delay slot scheduling have been done. This pass generally, but not always, improves performance and code size, at the cost of extra compilation time, which is why there is an option to switch it off. If you have a problem with call instructions exceeding their allowable offset range because they are conditionalized, you should consider using <samp class="option">-mmedium-calls</samp> instead. </p> </dd> <dt>
+<span><code class="code">-mearly-cbranchsi</code><a class="copiable-link" href="#index-mearly-cbranchsi"> ¶</a></span>
+</dt> <dd>
+<p>Enable pre-reload use of the <code class="code">cbranchsi</code> pattern. </p> </dd> <dt>
+<span><code class="code">-mexpand-adddi</code><a class="copiable-link" href="#index-mexpand-adddi"> ¶</a></span>
+</dt> <dd>
+<p>Expand <code class="code">adddi3</code> and <code class="code">subdi3</code> at RTL generation time into <code class="code">add.f</code>, <code class="code">adc</code> etc. This option is deprecated. </p> </dd> <dt>
+<span><code class="code">-mindexed-loads</code><a class="copiable-link" href="#index-mindexed-loads"> ¶</a></span>
+</dt> <dd>
+<p>Enable the use of indexed loads. This can be problematic because some optimizers then assume that indexed stores exist, which is not the case. </p> </dd> <dt>
+<span><code class="code">-mlra</code><a class="copiable-link" href="#index-mlra"> ¶</a></span>
+</dt> <dd>
+<p>Enable Local Register Allocation. This is still experimental for ARC, so by default the compiler uses standard reload (i.e. <samp class="option">-mno-lra</samp>). </p> </dd> <dt>
+<span><code class="code">-mlra-priority-none</code><a class="copiable-link" href="#index-mlra-priority-none"> ¶</a></span>
+</dt> <dd>
+<p>Don’t indicate any priority for target registers. </p> </dd> <dt>
+<span><code class="code">-mlra-priority-compact</code><a class="copiable-link" href="#index-mlra-priority-compact"> ¶</a></span>
+</dt> <dd>
+<p>Indicate target register priority for r0..r3 / r12..r15. </p> </dd> <dt>
+<span><code class="code">-mlra-priority-noncompact</code><a class="copiable-link" href="#index-mlra-priority-noncompact"> ¶</a></span>
+</dt> <dd>
+<p>Reduce target register priority for r0..r3 / r12..r15. </p> </dd> <dt>
+<span><code class="code">-mmillicode</code><a class="copiable-link" href="#index-mmillicode"> ¶</a></span>
+</dt> <dd>
+<p>When optimizing for size (using <samp class="option">-Os</samp>), prologues and epilogues that have to save or restore a large number of registers are often shortened by using call to a special function in libgcc; this is referred to as a <em class="emph">millicode</em> call. As these calls can pose performance issues, and/or cause linking issues when linking in a nonstandard way, this option is provided to turn on or off millicode call generation. </p> </dd> <dt>
+<span><code class="code">-mcode-density-frame</code><a class="copiable-link" href="#index-mcode-density-frame"> ¶</a></span>
+</dt> <dd>
+<p>This option enable the compiler to emit <code class="code">enter</code> and <code class="code">leave</code> instructions. These instructions are only valid for CPUs with code-density feature. </p> </dd> <dt>
+<span><code class="code">-mmixed-code</code><a class="copiable-link" href="#index-mmixed-code"> ¶</a></span>
+</dt> <dd>
+<p>Does nothing. Preserved for backward compatibility. </p> </dd> <dt>
+<span><code class="code">-mq-class</code><a class="copiable-link" href="#index-mq-class"> ¶</a></span>
+</dt> <dd>
+<p>Ths option is deprecated. Enable ‘<samp class="samp">q</samp>’ instruction alternatives. This is the default for <samp class="option">-Os</samp>. </p> </dd> <dt>
+<span><code class="code">-mRcq</code><a class="copiable-link" href="#index-mRcq"> ¶</a></span>
+</dt> <dd>
+<p>Does nothing. Preserved for backward compatibility. </p> </dd> <dt>
+<span><code class="code">-mRcw</code><a class="copiable-link" href="#index-mRcw"> ¶</a></span>
+</dt> <dd>
+<p>Does nothing. Preserved for backward compatibility. </p> </dd> <dt>
+<span><code class="code">-msize-level=<var class="var">level</var></code><a class="copiable-link" href="#index-msize-level"> ¶</a></span>
+</dt> <dd>
+<p>Fine-tune size optimization with regards to instruction lengths and alignment. The recognized values for <var class="var">level</var> are: </p>
+<dl class="table"> <dt>‘<samp class="samp">0</samp>’</dt> <dd>
+<p>No size optimization. This level is deprecated and treated like ‘<samp class="samp">1</samp>’. </p> </dd> <dt>‘<samp class="samp">1</samp>’</dt> <dd>
+<p>Short instructions are used opportunistically. </p> </dd> <dt>‘<samp class="samp">2</samp>’</dt> <dd>
+<p>In addition, alignment of loops and of code after barriers are dropped. </p> </dd> <dt>‘<samp class="samp">3</samp>’</dt> <dd>
+<p>In addition, optional data alignment is dropped, and the option <samp class="option">Os</samp> is enabled. </p> </dd> </dl> <p>This defaults to ‘<samp class="samp">3</samp>’ when <samp class="option">-Os</samp> is in effect. Otherwise, the behavior when this is not set is equivalent to level ‘<samp class="samp">1</samp>’. </p> </dd> <dt>
+<span><code class="code">-mtune=<var class="var">cpu</var></code><a class="copiable-link" href="#index-mtune-2"> ¶</a></span>
+</dt> <dd>
+<p>Set instruction scheduling parameters for <var class="var">cpu</var>, overriding any implied by <samp class="option">-mcpu=</samp>. </p> <p>Supported values for <var class="var">cpu</var> are </p> <dl class="table"> <dt>‘<samp class="samp">ARC600</samp>’</dt> <dd>
+<p>Tune for ARC600 CPU. </p> </dd> <dt>‘<samp class="samp">ARC601</samp>’</dt> <dd>
+<p>Tune for ARC601 CPU. </p> </dd> <dt>‘<samp class="samp">ARC700</samp>’</dt> <dd>
+<p>Tune for ARC700 CPU with standard multiplier block. </p> </dd> <dt>‘<samp class="samp">ARC700-xmac</samp>’</dt> <dd>
+<p>Tune for ARC700 CPU with XMAC block. </p> </dd> <dt>‘<samp class="samp">ARC725D</samp>’</dt> <dd>
+<p>Tune for ARC725D CPU. </p> </dd> <dt>‘<samp class="samp">ARC750D</samp>’</dt> <dd>
+<p>Tune for ARC750D CPU. </p> </dd> <dt>‘<samp class="samp">core3</samp>’</dt> <dd>
+<p>Tune for ARCv2 core3 type CPU. This option enable usage of <code class="code">dbnz</code> instruction. </p> </dd> <dt>‘<samp class="samp">release31a</samp>’</dt> <dd>
+<p>Tune for ARC4x release 3.10a. </p> </dd> </dl> </dd> <dt>
+<span><code class="code">-mmultcost=<var class="var">num</var></code><a class="copiable-link" href="#index-mmultcost"> ¶</a></span>
+</dt> <dd>
+<p>Cost to assume for a multiply instruction, with ‘<samp class="samp">4</samp>’ being equal to a normal instruction. </p> </dd> <dt>
+<span><code class="code">-munalign-prob-threshold=<var class="var">probability</var></code><a class="copiable-link" href="#index-munalign-prob-threshold"> ¶</a></span>
+</dt> <dd>
+<p>Does nothing. Preserved for backward compatibility. </p> </dd> </dl> <p>The following options are maintained for backward compatibility, but are now deprecated and will be removed in a future release: </p> <dl class="table"> <dt>
+<span><code class="code">-margonaut</code><a class="copiable-link" href="#index-margonaut"> ¶</a></span>
+</dt> <dd>
+<p>Obsolete FPX. </p> </dd> <dt>
+ <span><code class="code">-mbig-endian</code><a class="copiable-link" href="#index-mbig-endian-1"> ¶</a></span>
+</dt> <dt><code class="code">-EB</code></dt> <dd>
+<p>Compile code for big-endian targets. Use of these options is now deprecated. Big-endian code is supported by configuring GCC to build <code class="code">arceb-elf32</code> and <code class="code">arceb-linux-uclibc</code> targets, for which big endian is the default. </p> </dd> <dt>
+ <span><code class="code">-mlittle-endian</code><a class="copiable-link" href="#index-mlittle-endian-1"> ¶</a></span>
+</dt> <dt><code class="code">-EL</code></dt> <dd>
+<p>Compile code for little-endian targets. Use of these options is now deprecated. Little-endian code is supported by configuring GCC to build <code class="code">arc-elf32</code> and <code class="code">arc-linux-uclibc</code> targets, for which little endian is the default. </p> </dd> <dt>
+<span><code class="code">-mbarrel_shifter</code><a class="copiable-link" href="#index-mbarrel_005fshifter"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mbarrel-shifter</samp>. </p> </dd> <dt>
+<span><code class="code">-mdpfp_compact</code><a class="copiable-link" href="#index-mdpfp_005fcompact"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mdpfp-compact</samp>. </p> </dd> <dt>
+<span><code class="code">-mdpfp_fast</code><a class="copiable-link" href="#index-mdpfp_005ffast"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mdpfp-fast</samp>. </p> </dd> <dt>
+<span><code class="code">-mdsp_packa</code><a class="copiable-link" href="#index-mdsp_005fpacka"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mdsp-packa</samp>. </p> </dd> <dt>
+<span><code class="code">-mEA</code><a class="copiable-link" href="#index-mEA"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mea</samp>. </p> </dd> <dt>
+<span><code class="code">-mmac_24</code><a class="copiable-link" href="#index-mmac_005f24"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mmac-24</samp>. </p> </dd> <dt>
+<span><code class="code">-mmac_d16</code><a class="copiable-link" href="#index-mmac_005fd16"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mmac-d16</samp>. </p> </dd> <dt>
+<span><code class="code">-mspfp_compact</code><a class="copiable-link" href="#index-mspfp_005fcompact"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mspfp-compact</samp>. </p> </dd> <dt>
+<span><code class="code">-mspfp_fast</code><a class="copiable-link" href="#index-mspfp_005ffast"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mspfp-fast</samp>. </p> </dd> <dt>
+<span><code class="code">-mtune=<var class="var">cpu</var></code><a class="copiable-link" href="#index-mtune-3"> ¶</a></span>
+</dt> <dd>
+<p>Values ‘<samp class="samp">arc600</samp>’, ‘<samp class="samp">arc601</samp>’, ‘<samp class="samp">arc700</samp>’ and ‘<samp class="samp">arc700-xmac</samp>’ for <var class="var">cpu</var> are replaced by ‘<samp class="samp">ARC600</samp>’, ‘<samp class="samp">ARC601</samp>’, ‘<samp class="samp">ARC700</samp>’ and ‘<samp class="samp">ARC700-xmac</samp>’ respectively. </p> </dd> <dt>
+<span><code class="code">-multcost=<var class="var">num</var></code><a class="copiable-link" href="#index-multcost"> ¶</a></span>
+</dt> <dd>
+<p>Replaced by <samp class="option">-mmultcost</samp>. </p> </dd> </dl> </div>  <div class="nav-panel"> <p> Next: <a href="arm-options">ARM Options</a>, Previous: <a href="amd-gcn-options">AMD GCN Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
+  <p class="_attribution-p">
+    &copy; Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
+    <a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/ARC-Options.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/ARC-Options.html</a>
+  </p>
+</div>