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+<div class="subsection-level-extent" id="M680x0-Options"> <div class="nav-panel"> <p> Next: <a href="mcore-options" accesskey="n" rel="next">MCore Options</a>, Previous: <a href="m32r_002fd-options" accesskey="p" rel="prev">M32R/D Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="M680x0-Options-1"><span>3.19.25 M680x0 Options<a class="copiable-link" href="#M680x0-Options-1"> ¶</a></span></h1>  <p>These are the ‘<samp class="samp">-m</samp>’ options defined for M680x0 and ColdFire processors. The default settings depend on which architecture was selected when the compiler was configured; the defaults for the most common choices are given below. </p> <dl class="table"> <dt>
+<span><code class="code">-march=<var class="var">arch</var></code><a class="copiable-link" href="#index-march-8"> ¶</a></span>
+</dt> <dd>
+<p>Generate code for a specific M680x0 or ColdFire instruction set architecture. Permissible values of <var class="var">arch</var> for M680x0 architectures are: ‘<samp class="samp">68000</samp>’, ‘<samp class="samp">68010</samp>’, ‘<samp class="samp">68020</samp>’, ‘<samp class="samp">68030</samp>’, ‘<samp class="samp">68040</samp>’, ‘<samp class="samp">68060</samp>’ and ‘<samp class="samp">cpu32</samp>’. ColdFire architectures are selected according to Freescale’s ISA classification and the permissible values are: ‘<samp class="samp">isaa</samp>’, ‘<samp class="samp">isaaplus</samp>’, ‘<samp class="samp">isab</samp>’ and ‘<samp class="samp">isac</samp>’. </p> <p>GCC defines a macro <code class="code">__mcf<var class="var">arch</var>__</code> whenever it is generating code for a ColdFire target. The <var class="var">arch</var> in this macro is one of the <samp class="option">-march</samp> arguments given above. </p> <p>When used together, <samp class="option">-march</samp> and <samp class="option">-mtune</samp> select code that runs on a family of similar processors but that is optimized for a particular microarchitecture. </p> </dd> <dt>
+<span><code class="code">-mcpu=<var class="var">cpu</var></code><a class="copiable-link" href="#index-mcpu-7"> ¶</a></span>
+</dt> <dd>
+<p>Generate code for a specific M680x0 or ColdFire processor. The M680x0 <var class="var">cpu</var>s are: ‘<samp class="samp">68000</samp>’, ‘<samp class="samp">68010</samp>’, ‘<samp class="samp">68020</samp>’, ‘<samp class="samp">68030</samp>’, ‘<samp class="samp">68040</samp>’, ‘<samp class="samp">68060</samp>’, ‘<samp class="samp">68302</samp>’, ‘<samp class="samp">68332</samp>’ and ‘<samp class="samp">cpu32</samp>’. The ColdFire <var class="var">cpu</var>s are given by the table below, which also classifies the CPUs into families: </p> <table class="multitable"> <thead><tr>
+<th width="20%"><strong class="strong">Family</strong></th>
+<th width="80%"><strong class="strong">‘<samp class="samp">-mcpu</samp>’ arguments</strong></th>
+</tr></thead> <tbody>
+<tr>
+<td width="20%">‘<samp class="samp">51</samp>’</td>
+<td width="80%">‘<samp class="samp">51</samp>’ ‘<samp class="samp">51ac</samp>’ ‘<samp class="samp">51ag</samp>’ ‘<samp class="samp">51cn</samp>’ ‘<samp class="samp">51em</samp>’ ‘<samp class="samp">51je</samp>’ ‘<samp class="samp">51jf</samp>’ ‘<samp class="samp">51jg</samp>’ ‘<samp class="samp">51jm</samp>’ ‘<samp class="samp">51mm</samp>’ ‘<samp class="samp">51qe</samp>’ ‘<samp class="samp">51qm</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5206</samp>’</td>
+<td width="80%">‘<samp class="samp">5202</samp>’ ‘<samp class="samp">5204</samp>’ ‘<samp class="samp">5206</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5206e</samp>’</td>
+<td width="80%">‘<samp class="samp">5206e</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5208</samp>’</td>
+<td width="80%">‘<samp class="samp">5207</samp>’ ‘<samp class="samp">5208</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5211a</samp>’</td>
+<td width="80%">‘<samp class="samp">5210a</samp>’ ‘<samp class="samp">5211a</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5213</samp>’</td>
+<td width="80%">‘<samp class="samp">5211</samp>’ ‘<samp class="samp">5212</samp>’ ‘<samp class="samp">5213</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5216</samp>’</td>
+<td width="80%">‘<samp class="samp">5214</samp>’ ‘<samp class="samp">5216</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">52235</samp>’</td>
+<td width="80%">‘<samp class="samp">52230</samp>’ ‘<samp class="samp">52231</samp>’ ‘<samp class="samp">52232</samp>’ ‘<samp class="samp">52233</samp>’ ‘<samp class="samp">52234</samp>’ ‘<samp class="samp">52235</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5225</samp>’</td>
+<td width="80%">‘<samp class="samp">5224</samp>’ ‘<samp class="samp">5225</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">52259</samp>’</td>
+<td width="80%">‘<samp class="samp">52252</samp>’ ‘<samp class="samp">52254</samp>’ ‘<samp class="samp">52255</samp>’ ‘<samp class="samp">52256</samp>’ ‘<samp class="samp">52258</samp>’ ‘<samp class="samp">52259</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5235</samp>’</td>
+<td width="80%">‘<samp class="samp">5232</samp>’ ‘<samp class="samp">5233</samp>’ ‘<samp class="samp">5234</samp>’ ‘<samp class="samp">5235</samp>’ ‘<samp class="samp">523x</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5249</samp>’</td>
+<td width="80%">‘<samp class="samp">5249</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5250</samp>’</td>
+<td width="80%">‘<samp class="samp">5250</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5271</samp>’</td>
+<td width="80%">‘<samp class="samp">5270</samp>’ ‘<samp class="samp">5271</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5272</samp>’</td>
+<td width="80%">‘<samp class="samp">5272</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5275</samp>’</td>
+<td width="80%">‘<samp class="samp">5274</samp>’ ‘<samp class="samp">5275</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5282</samp>’</td>
+<td width="80%">‘<samp class="samp">5280</samp>’ ‘<samp class="samp">5281</samp>’ ‘<samp class="samp">5282</samp>’ ‘<samp class="samp">528x</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">53017</samp>’</td>
+<td width="80%">‘<samp class="samp">53011</samp>’ ‘<samp class="samp">53012</samp>’ ‘<samp class="samp">53013</samp>’ ‘<samp class="samp">53014</samp>’ ‘<samp class="samp">53015</samp>’ ‘<samp class="samp">53016</samp>’ ‘<samp class="samp">53017</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5307</samp>’</td>
+<td width="80%">‘<samp class="samp">5307</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5329</samp>’</td>
+<td width="80%">‘<samp class="samp">5327</samp>’ ‘<samp class="samp">5328</samp>’ ‘<samp class="samp">5329</samp>’ ‘<samp class="samp">532x</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5373</samp>’</td>
+<td width="80%">‘<samp class="samp">5372</samp>’ ‘<samp class="samp">5373</samp>’ ‘<samp class="samp">537x</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5407</samp>’</td>
+<td width="80%">‘<samp class="samp">5407</samp>’</td>
+</tr> <tr>
+<td width="20%">‘<samp class="samp">5475</samp>’</td>
+<td width="80%">‘<samp class="samp">5470</samp>’ ‘<samp class="samp">5471</samp>’ ‘<samp class="samp">5472</samp>’ ‘<samp class="samp">5473</samp>’ ‘<samp class="samp">5474</samp>’ ‘<samp class="samp">5475</samp>’ ‘<samp class="samp">547x</samp>’ ‘<samp class="samp">5480</samp>’ ‘<samp class="samp">5481</samp>’ ‘<samp class="samp">5482</samp>’ ‘<samp class="samp">5483</samp>’ ‘<samp class="samp">5484</samp>’ ‘<samp class="samp">5485</samp>’</td>
+</tr> </tbody> </table> <p><samp class="option">-mcpu=<var class="var">cpu</var></samp> overrides <samp class="option">-march=<var class="var">arch</var></samp> if <var class="var">arch</var> is compatible with <var class="var">cpu</var>. Other combinations of <samp class="option">-mcpu</samp> and <samp class="option">-march</samp> are rejected. </p> <p>GCC defines the macro <code class="code">__mcf_cpu_<var class="var">cpu</var></code> when ColdFire target <var class="var">cpu</var> is selected. It also defines <code class="code">__mcf_family_<var class="var">family</var></code>, where the value of <var class="var">family</var> is given by the table above. </p> </dd> <dt>
+<span><code class="code">-mtune=<var class="var">tune</var></code><a class="copiable-link" href="#index-mtune-9"> ¶</a></span>
+</dt> <dd>
+<p>Tune the code for a particular microarchitecture within the constraints set by <samp class="option">-march</samp> and <samp class="option">-mcpu</samp>. The M680x0 microarchitectures are: ‘<samp class="samp">68000</samp>’, ‘<samp class="samp">68010</samp>’, ‘<samp class="samp">68020</samp>’, ‘<samp class="samp">68030</samp>’, ‘<samp class="samp">68040</samp>’, ‘<samp class="samp">68060</samp>’ and ‘<samp class="samp">cpu32</samp>’. The ColdFire microarchitectures are: ‘<samp class="samp">cfv1</samp>’, ‘<samp class="samp">cfv2</samp>’, ‘<samp class="samp">cfv3</samp>’, ‘<samp class="samp">cfv4</samp>’ and ‘<samp class="samp">cfv4e</samp>’. </p> <p>You can also use <samp class="option">-mtune=68020-40</samp> for code that needs to run relatively well on 68020, 68030 and 68040 targets. <samp class="option">-mtune=68020-60</samp> is similar but includes 68060 targets as well. These two options select the same tuning decisions as <samp class="option">-m68020-40</samp> and <samp class="option">-m68020-60</samp> respectively. </p> <p>GCC defines the macros <code class="code">__mc<var class="var">arch</var></code> and <code class="code">__mc<var class="var">arch</var>__</code> when tuning for 680x0 architecture <var class="var">arch</var>. It also defines <code class="code">mc<var class="var">arch</var></code> unless either <samp class="option">-ansi</samp> or a non-GNU <samp class="option">-std</samp> option is used. If GCC is tuning for a range of architectures, as selected by <samp class="option">-mtune=68020-40</samp> or <samp class="option">-mtune=68020-60</samp>, it defines the macros for every architecture in the range. </p> <p>GCC also defines the macro <code class="code">__m<var class="var">uarch</var>__</code> when tuning for ColdFire microarchitecture <var class="var">uarch</var>, where <var class="var">uarch</var> is one of the arguments given above. </p> </dd> <dt>
+ <span><code class="code">-m68000</code><a class="copiable-link" href="#index-m68000"> ¶</a></span>
+</dt> <dt><code class="code">-mc68000</code></dt> <dd>
+<p>Generate output for a 68000. This is the default when the compiler is configured for 68000-based systems. It is equivalent to <samp class="option">-march=68000</samp>. </p> <p>Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. </p> </dd> <dt>
+<span><code class="code">-m68010</code><a class="copiable-link" href="#index-m68010"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 68010. This is the default when the compiler is configured for 68010-based systems. It is equivalent to <samp class="option">-march=68010</samp>. </p> </dd> <dt>
+ <span><code class="code">-m68020</code><a class="copiable-link" href="#index-m68020"> ¶</a></span>
+</dt> <dt><code class="code">-mc68020</code></dt> <dd>
+<p>Generate output for a 68020. This is the default when the compiler is configured for 68020-based systems. It is equivalent to <samp class="option">-march=68020</samp>. </p> </dd> <dt>
+<span><code class="code">-m68030</code><a class="copiable-link" href="#index-m68030"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 68030. This is the default when the compiler is configured for 68030-based systems. It is equivalent to <samp class="option">-march=68030</samp>. </p> </dd> <dt>
+<span><code class="code">-m68040</code><a class="copiable-link" href="#index-m68040"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 68040. This is the default when the compiler is configured for 68040-based systems. It is equivalent to <samp class="option">-march=68040</samp>. </p> <p>This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040. Use this option if your 68040 does not have code to emulate those instructions. </p> </dd> <dt>
+<span><code class="code">-m68060</code><a class="copiable-link" href="#index-m68060"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 68060. This is the default when the compiler is configured for 68060-based systems. It is equivalent to <samp class="option">-march=68060</samp>. </p> <p>This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions. </p> </dd> <dt>
+<span><code class="code">-mcpu32</code><a class="copiable-link" href="#index-mcpu32"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a CPU32. This is the default when the compiler is configured for CPU32-based systems. It is equivalent to <samp class="option">-march=cpu32</samp>. </p> <p>Use this option for microcontrollers with a CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349 and 68360. </p> </dd> <dt>
+<span><code class="code">-m5200</code><a class="copiable-link" href="#index-m5200"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 520X ColdFire CPU. This is the default when the compiler is configured for 520X-based systems. It is equivalent to <samp class="option">-mcpu=5206</samp>, and is now deprecated in favor of that option. </p> <p>Use this option for microcontroller with a 5200 core, including the MCF5202, MCF5203, MCF5204 and MCF5206. </p> </dd> <dt>
+<span><code class="code">-m5206e</code><a class="copiable-link" href="#index-m5206e"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 5206e ColdFire CPU. The option is now deprecated in favor of the equivalent <samp class="option">-mcpu=5206e</samp>. </p> </dd> <dt>
+<span><code class="code">-m528x</code><a class="copiable-link" href="#index-m528x"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a member of the ColdFire 528X family. The option is now deprecated in favor of the equivalent <samp class="option">-mcpu=528x</samp>. </p> </dd> <dt>
+<span><code class="code">-m5307</code><a class="copiable-link" href="#index-m5307"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a ColdFire 5307 CPU. The option is now deprecated in favor of the equivalent <samp class="option">-mcpu=5307</samp>. </p> </dd> <dt>
+<span><code class="code">-m5407</code><a class="copiable-link" href="#index-m5407"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a ColdFire 5407 CPU. The option is now deprecated in favor of the equivalent <samp class="option">-mcpu=5407</samp>. </p> </dd> <dt>
+<span><code class="code">-mcfv4e</code><a class="copiable-link" href="#index-mcfv4e"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to <samp class="option">-mcpu=547x</samp>, and is now deprecated in favor of that option. </p> </dd> <dt>
+<span><code class="code">-m68020-40</code><a class="copiable-link" href="#index-m68020-40"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 68040, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68040. </p> <p>The option is equivalent to <samp class="option">-march=68020</samp> <samp class="option">-mtune=68020-40</samp>. </p> </dd> <dt>
+<span><code class="code">-m68020-60</code><a class="copiable-link" href="#index-m68020-60"> ¶</a></span>
+</dt> <dd>
+<p>Generate output for a 68060, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68060. </p> <p>The option is equivalent to <samp class="option">-march=68020</samp> <samp class="option">-mtune=68020-60</samp>. </p> </dd> <dt>
+ <span><code class="code">-mhard-float</code><a class="copiable-link" href="#index-mhard-float-2"> ¶</a></span>
+</dt> <dt><code class="code">-m68881</code></dt> <dd>
+<p>Generate floating-point instructions. This is the default for 68020 and above, and for ColdFire devices that have an FPU. It defines the macro <code class="code">__HAVE_68881__</code> on M680x0 targets and <code class="code">__mcffpu__</code> on ColdFire targets. </p> </dd> <dt>
+<span><code class="code">-msoft-float</code><a class="copiable-link" href="#index-msoft-float-6"> ¶</a></span>
+</dt> <dd>
+<p>Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 68010, and 68832 targets. It is also the default for ColdFire devices that have no FPU. </p> </dd> <dt>
+ <span><code class="code">-mdiv</code><a class="copiable-link" href="#index-mdiv-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-div</code></dt> <dd>
+<p>Generate (do not generate) ColdFire hardware divide and remainder instructions. If <samp class="option">-march</samp> is used without <samp class="option">-mcpu</samp>, the default is “on” for ColdFire architectures and “off” for M680x0 architectures. Otherwise, the default is taken from the target CPU (either the default CPU, or the one specified by <samp class="option">-mcpu</samp>). For example, the default is “off” for <samp class="option">-mcpu=5206</samp> and “on” for <samp class="option">-mcpu=5206e</samp>. </p> <p>GCC defines the macro <code class="code">__mcfhwdiv__</code> when this option is enabled. </p> </dd> <dt>
+<span><code class="code">-mshort</code><a class="copiable-link" href="#index-mshort"> ¶</a></span>
+</dt> <dd>
+<p>Consider type <code class="code">int</code> to be 16 bits wide, like <code class="code">short int</code>. Additionally, parameters passed on the stack are also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit. </p> </dd> <dt>
+<span><code class="code">-mno-short</code><a class="copiable-link" href="#index-mno-short"> ¶</a></span>
+</dt> <dd>
+<p>Do not consider type <code class="code">int</code> to be 16 bits wide. This is the default. </p> </dd> <dt>
+ <span><code class="code">-mnobitfield</code><a class="copiable-link" href="#index-mnobitfield"> ¶</a></span>
+</dt> <dt><code class="code">-mno-bitfield</code></dt> <dd>
+<p>Do not use the bit-field instructions. The <samp class="option">-m68000</samp>, <samp class="option">-mcpu32</samp> and <samp class="option">-m5200</samp> options imply <samp class="option">-mnobitfield</samp>. </p> </dd> <dt>
+<span><code class="code">-mbitfield</code><a class="copiable-link" href="#index-mbitfield"> ¶</a></span>
+</dt> <dd>
+<p>Do use the bit-field instructions. The <samp class="option">-m68020</samp> option implies <samp class="option">-mbitfield</samp>. This is the default if you use a configuration designed for a 68020. </p> </dd> <dt>
+<span><code class="code">-mrtd</code><a class="copiable-link" href="#index-mrtd"> ¶</a></span>
+</dt> <dd>
+<p>Use a different function-calling convention, in which functions that take a fixed number of arguments return with the <code class="code">rtd</code> instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop the arguments there. </p> <p>This calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler. </p> <p>Also, you must provide function prototypes for all functions that take variable numbers of arguments (including <code class="code">printf</code>); otherwise incorrect code is generated for calls to those functions. </p> <p>In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, extra arguments are harmlessly ignored.) </p> <p>The <code class="code">rtd</code> instruction is supported by the 68010, 68020, 68030, 68040, 68060 and CPU32 processors, but not by the 68000 or 5200. </p> <p>The default is <samp class="option">-mno-rtd</samp>. </p> </dd> <dt>
+ <span><code class="code">-malign-int</code><a class="copiable-link" href="#index-malign-int"> ¶</a></span>
+</dt> <dt><code class="code">-mno-align-int</code></dt> <dd>
+<p>Control whether GCC aligns <code class="code">int</code>, <code class="code">long</code>, <code class="code">long long</code>, <code class="code">float</code>, <code class="code">double</code>, and <code class="code">long double</code> variables on a 32-bit boundary (<samp class="option">-malign-int</samp>) or a 16-bit boundary (<samp class="option">-mno-align-int</samp>). Aligning variables on 32-bit boundaries produces code that runs somewhat faster on processors with 32-bit busses at the expense of more memory. </p> <p><strong class="strong">Warning:</strong> if you use the <samp class="option">-malign-int</samp> switch, GCC aligns structures containing the above types differently than most published application binary interface specifications for the m68k. </p>  <p>Use the pc-relative addressing mode of the 68000 directly, instead of using a global offset table. At present, this option implies <samp class="option">-fpic</samp>, allowing at most a 16-bit offset for pc-relative addressing. <samp class="option">-fPIC</samp> is not presently supported with <samp class="option">-mpcrel</samp>, though this could be supported for 68020 and higher processors. </p> </dd> <dt>
+ <span><code class="code">-mno-strict-align</code><a class="copiable-link" href="#index-mno-strict-align-1"> ¶</a></span>
+</dt> <dt><code class="code">-mstrict-align</code></dt> <dd>
+<p>Do not (do) assume that unaligned memory references are handled by the system. </p> </dd> <dt><code class="code">-msep-data</code></dt> <dd>
+<p>Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute-in-place in an environment without virtual memory management. This option implies <samp class="option">-fPIC</samp>. </p> </dd> <dt><code class="code">-mno-sep-data</code></dt> <dd>
+<p>Generate code that assumes that the data segment follows the text segment. This is the default. </p> </dd> <dt><code class="code">-mid-shared-library</code></dt> <dd>
+<p>Generate code that supports shared libraries via the library ID method. This allows for execute-in-place and shared libraries in an environment without virtual memory management. This option implies <samp class="option">-fPIC</samp>. </p> </dd> <dt><code class="code">-mno-id-shared-library</code></dt> <dd>
+<p>Generate code that doesn’t assume ID-based shared libraries are being used. This is the default. </p> </dd> <dt><code class="code">-mshared-library-id=n</code></dt> <dd>
+<p>Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library, but is no more space- or time-efficient than omitting this option. </p> </dd> <dt>
+ <span><code class="code">-mxgot</code><a class="copiable-link" href="#index-mxgot"> ¶</a></span>
+</dt> <dt><code class="code">-mno-xgot</code></dt> <dd>
+<p>When generating position-independent code for ColdFire, generate code that works if the GOT has more than 8192 entries. This code is larger and slower than code generated without this option. On M680x0 processors, this option is not needed; <samp class="option">-fPIC</samp> suffices. </p> <p>GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as: </p>  <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">relocation truncated to fit: R_68K_GOT16O foobar</pre>
+</div> <p>If this happens, you should recompile your code with <samp class="option">-mxgot</samp>. It should then work with very large GOTs. However, code generated with <samp class="option">-mxgot</samp> is less efficient, since it takes 4 instructions to fetch the value of a global symbol. </p> <p>Note that some linkers, including newer versions of the GNU linker, can create multiple GOTs and sort GOT entries. If you have such a linker, you should only need to use <samp class="option">-mxgot</samp> when compiling a single object file that accesses more than 8192 GOT entries. Very few do. </p> <p>These options have no effect unless GCC is generating position-independent code. </p> </dd> <dt>
+<span><code class="code">-mlong-jump-table-offsets</code><a class="copiable-link" href="#index-mlong-jump-table-offsets"> ¶</a></span>
+</dt> <dd>
+<p>Use 32-bit offsets in <code class="code">switch</code> tables. The default is to use 16-bit offsets. </p> </dd> </dl> </div>  <div class="nav-panel"> <p> Next: <a href="mcore-options">MCore Options</a>, Previous: <a href="m32r_002fd-options">M32R/D Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
+  <p class="_attribution-p">
+    &copy; Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
+    <a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/M680x0-Options.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/M680x0-Options.html</a>
+  </p>
+</div>