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+<div class="subsection-level-extent" id="MIPS-Options"> <div class="nav-panel"> <p> Next: <a href="mmix-options" accesskey="n" rel="next">MMIX Options</a>, Previous: <a href="microblaze-options" accesskey="p" rel="prev">MicroBlaze Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="MIPS-Options-1"><span>3.19.28 MIPS Options<a class="copiable-link" href="#MIPS-Options-1"> ¶</a></span></h1>  <dl class="table"> <dt>
+<span><code class="code">-EB</code><a class="copiable-link" href="#index-EB-2"> ¶</a></span>
+</dt> <dd>
+<p>Generate big-endian code. </p> </dd> <dt>
+<span><code class="code">-EL</code><a class="copiable-link" href="#index-EL-2"> ¶</a></span>
+</dt> <dd>
+<p>Generate little-endian code. This is the default for ‘<samp class="samp">mips*el-*-*</samp>’ configurations. </p> </dd> <dt>
+<span><code class="code">-march=<var class="var">arch</var></code><a class="copiable-link" href="#index-march-9"> ¶</a></span>
+</dt> <dd>
+<p>Generate code that runs on <var class="var">arch</var>, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: ‘<samp class="samp">mips1</samp>’, ‘<samp class="samp">mips2</samp>’, ‘<samp class="samp">mips3</samp>’, ‘<samp class="samp">mips4</samp>’, ‘<samp class="samp">mips32</samp>’, ‘<samp class="samp">mips32r2</samp>’, ‘<samp class="samp">mips32r3</samp>’, ‘<samp class="samp">mips32r5</samp>’, ‘<samp class="samp">mips32r6</samp>’, ‘<samp class="samp">mips64</samp>’, ‘<samp class="samp">mips64r2</samp>’, ‘<samp class="samp">mips64r3</samp>’, ‘<samp class="samp">mips64r5</samp>’ and ‘<samp class="samp">mips64r6</samp>’. The processor names are: ‘<samp class="samp">4kc</samp>’, ‘<samp class="samp">4km</samp>’, ‘<samp class="samp">4kp</samp>’, ‘<samp class="samp">4ksc</samp>’, ‘<samp class="samp">4kec</samp>’, ‘<samp class="samp">4kem</samp>’, ‘<samp class="samp">4kep</samp>’, ‘<samp class="samp">4ksd</samp>’, ‘<samp class="samp">5kc</samp>’, ‘<samp class="samp">5kf</samp>’, ‘<samp class="samp">20kc</samp>’, ‘<samp class="samp">24kc</samp>’, ‘<samp class="samp">24kf2_1</samp>’, ‘<samp class="samp">24kf1_1</samp>’, ‘<samp class="samp">24kec</samp>’, ‘<samp class="samp">24kef2_1</samp>’, ‘<samp class="samp">24kef1_1</samp>’, ‘<samp class="samp">34kc</samp>’, ‘<samp class="samp">34kf2_1</samp>’, ‘<samp class="samp">34kf1_1</samp>’, ‘<samp class="samp">34kn</samp>’, ‘<samp class="samp">74kc</samp>’, ‘<samp class="samp">74kf2_1</samp>’, ‘<samp class="samp">74kf1_1</samp>’, ‘<samp class="samp">74kf3_2</samp>’, ‘<samp class="samp">1004kc</samp>’, ‘<samp class="samp">1004kf2_1</samp>’, ‘<samp class="samp">1004kf1_1</samp>’, ‘<samp class="samp">i6400</samp>’, ‘<samp class="samp">i6500</samp>’, ‘<samp class="samp">interaptiv</samp>’, ‘<samp class="samp">loongson2e</samp>’, ‘<samp class="samp">loongson2f</samp>’, ‘<samp class="samp">loongson3a</samp>’, ‘<samp class="samp">gs464</samp>’, ‘<samp class="samp">gs464e</samp>’, ‘<samp class="samp">gs264e</samp>’, ‘<samp class="samp">m4k</samp>’, ‘<samp class="samp">m14k</samp>’, ‘<samp class="samp">m14kc</samp>’, ‘<samp class="samp">m14ke</samp>’, ‘<samp class="samp">m14kec</samp>’, ‘<samp class="samp">m5100</samp>’, ‘<samp class="samp">m5101</samp>’, ‘<samp class="samp">octeon</samp>’, ‘<samp class="samp">octeon+</samp>’, ‘<samp class="samp">octeon2</samp>’, ‘<samp class="samp">octeon3</samp>’, ‘<samp class="samp">orion</samp>’, ‘<samp class="samp">p5600</samp>’, ‘<samp class="samp">p6600</samp>’, ‘<samp class="samp">r2000</samp>’, ‘<samp class="samp">r3000</samp>’, ‘<samp class="samp">r3900</samp>’, ‘<samp class="samp">r4000</samp>’, ‘<samp class="samp">r4400</samp>’, ‘<samp class="samp">r4600</samp>’, ‘<samp class="samp">r4650</samp>’, ‘<samp class="samp">r4700</samp>’, ‘<samp class="samp">r5900</samp>’, ‘<samp class="samp">r6000</samp>’, ‘<samp class="samp">r8000</samp>’, ‘<samp class="samp">rm7000</samp>’, ‘<samp class="samp">rm9000</samp>’, ‘<samp class="samp">r10000</samp>’, ‘<samp class="samp">r12000</samp>’, ‘<samp class="samp">r14000</samp>’, ‘<samp class="samp">r16000</samp>’, ‘<samp class="samp">sb1</samp>’, ‘<samp class="samp">sr71000</samp>’, ‘<samp class="samp">vr4100</samp>’, ‘<samp class="samp">vr4111</samp>’, ‘<samp class="samp">vr4120</samp>’, ‘<samp class="samp">vr4130</samp>’, ‘<samp class="samp">vr4300</samp>’, ‘<samp class="samp">vr5000</samp>’, ‘<samp class="samp">vr5400</samp>’, ‘<samp class="samp">vr5500</samp>’, ‘<samp class="samp">xlr</samp>’ and ‘<samp class="samp">xlp</samp>’. The special value ‘<samp class="samp">from-abi</samp>’ selects the most compatible architecture for the selected ABI (that is, ‘<samp class="samp">mips1</samp>’ for 32-bit ABIs and ‘<samp class="samp">mips3</samp>’ for 64-bit ABIs). </p> <p>The native Linux/GNU toolchain also supports the value ‘<samp class="samp">native</samp>’, which selects the best architecture option for the host processor. <samp class="option">-march=native</samp> has no effect if GCC does not recognize the processor. </p> <p>In processor names, a final ‘<samp class="samp">000</samp>’ can be abbreviated as ‘<samp class="samp">k</samp>’ (for example, <samp class="option">-march=r2k</samp>). Prefixes are optional, and ‘<samp class="samp">vr</samp>’ may be written ‘<samp class="samp">r</samp>’. </p> <p>Names of the form ‘<samp class="samp"><var class="var">n</var>f2_1</samp>’ refer to processors with FPUs clocked at half the rate of the core, names of the form ‘<samp class="samp"><var class="var">n</var>f1_1</samp>’ refer to processors with FPUs clocked at the same rate as the core, and names of the form ‘<samp class="samp"><var class="var">n</var>f3_2</samp>’ refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, ‘<samp class="samp"><var class="var">n</var>f</samp>’ is accepted as a synonym for ‘<samp class="samp"><var class="var">n</var>f2_1</samp>’ while ‘<samp class="samp"><var class="var">n</var>x</samp>’ and ‘<samp class="samp"><var class="var">b</var>fx</samp>’ are accepted as synonyms for ‘<samp class="samp"><var class="var">n</var>f1_1</samp>’. </p> <p>GCC defines two macros based on the value of this option. The first is <code class="code">_MIPS_ARCH</code>, which gives the name of target architecture, as a string. The second has the form <code class="code">_MIPS_ARCH_<var class="var">foo</var></code>, where <var class="var">foo</var> is the capitalized value of <code class="code">_MIPS_ARCH</code>. For example, <samp class="option">-march=r2000</samp> sets <code class="code">_MIPS_ARCH</code> to <code class="code">"r2000"</code> and defines the macro <code class="code">_MIPS_ARCH_R2000</code>. </p> <p>Note that the <code class="code">_MIPS_ARCH</code> macro uses the processor names given above. In other words, it has the full prefix and does not abbreviate ‘<samp class="samp">000</samp>’ as ‘<samp class="samp">k</samp>’. In the case of ‘<samp class="samp">from-abi</samp>’, the macro names the resolved architecture (either <code class="code">"mips1"</code> or <code class="code">"mips3"</code>). It names the default architecture when no <samp class="option">-march</samp> option is given. </p> </dd> <dt>
+<span><code class="code">-mtune=<var class="var">arch</var></code><a class="copiable-link" href="#index-mtune-10"> ¶</a></span>
+</dt> <dd>
+<p>Optimize for <var class="var">arch</var>. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of <var class="var">arch</var> values is the same as for <samp class="option">-march</samp>. </p> <p>When this option is not used, GCC optimizes for the processor specified by <samp class="option">-march</samp>. By using <samp class="option">-march</samp> and <samp class="option">-mtune</samp> together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family. </p> <p><samp class="option">-mtune</samp> defines the macros <code class="code">_MIPS_TUNE</code> and <code class="code">_MIPS_TUNE_<var class="var">foo</var></code>, which work in the same way as the <samp class="option">-march</samp> ones described above. </p> </dd> <dt>
+<span><code class="code">-mips1</code><a class="copiable-link" href="#index-mips1"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips1</samp>. </p> </dd> <dt>
+<span><code class="code">-mips2</code><a class="copiable-link" href="#index-mips2"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips2</samp>. </p> </dd> <dt>
+<span><code class="code">-mips3</code><a class="copiable-link" href="#index-mips3"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips3</samp>. </p> </dd> <dt>
+<span><code class="code">-mips4</code><a class="copiable-link" href="#index-mips4"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips4</samp>. </p> </dd> <dt>
+<span><code class="code">-mips32</code><a class="copiable-link" href="#index-mips32"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips32</samp>. </p> </dd> <dt>
+<span><code class="code">-mips32r3</code><a class="copiable-link" href="#index-mips32r3"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips32r3</samp>. </p> </dd> <dt>
+<span><code class="code">-mips32r5</code><a class="copiable-link" href="#index-mips32r5"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips32r5</samp>. </p> </dd> <dt>
+<span><code class="code">-mips32r6</code><a class="copiable-link" href="#index-mips32r6"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips32r6</samp>. </p> </dd> <dt>
+<span><code class="code">-mips64</code><a class="copiable-link" href="#index-mips64"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips64</samp>. </p> </dd> <dt>
+<span><code class="code">-mips64r2</code><a class="copiable-link" href="#index-mips64r2"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips64r2</samp>. </p> </dd> <dt>
+<span><code class="code">-mips64r3</code><a class="copiable-link" href="#index-mips64r3"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips64r3</samp>. </p> </dd> <dt>
+<span><code class="code">-mips64r5</code><a class="copiable-link" href="#index-mips64r5"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips64r5</samp>. </p> </dd> <dt>
+<span><code class="code">-mips64r6</code><a class="copiable-link" href="#index-mips64r6"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-march=mips64r6</samp>. </p> </dd> <dt>
+ <span><code class="code">-mips16</code><a class="copiable-link" href="#index-mips16"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mips16</code></dt> <dd>
+<p>Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE. </p> <p>MIPS16 code generation can also be controlled on a per-function basis by means of <code class="code">mips16</code> and <code class="code">nomips16</code> attributes. See <a class="xref" href="function-attributes">Declaring Attributes of Functions</a>, for more information. </p> </dd> <dt>
+<span><code class="code">-mflip-mips16</code><a class="copiable-link" href="#index-mflip-mips16"> ¶</a></span>
+</dt> <dd>
+<p>Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code. </p> </dd> <dt>
+ <span><code class="code">-minterlink-compressed</code><a class="copiable-link" href="#index-minterlink-compressed"> ¶</a></span>
+</dt> <dt><code class="code">-mno-interlink-compressed</code></dt> <dd>
+<p>Require (do not require) that code using the standard (uncompressed) MIPS ISA be link-compatible with MIPS16 and microMIPS code, and vice versa. </p> <p>For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must either use a call or an indirect jump. <samp class="option">-minterlink-compressed</samp> therefore disables direct jumps unless GCC knows that the target of the jump is not compressed. </p> </dd> <dt>
+ <span><code class="code">-minterlink-mips16</code><a class="copiable-link" href="#index-minterlink-mips16"> ¶</a></span>
+</dt> <dt><code class="code">-mno-interlink-mips16</code></dt> <dd>
+<p>Aliases of <samp class="option">-minterlink-compressed</samp> and <samp class="option">-mno-interlink-compressed</samp>. These options predate the microMIPS ASE and are retained for backwards compatibility. </p> </dd> <dt>
+    <span><code class="code">-mabi=32</code><a class="copiable-link" href="#index-mabi_003d32"> ¶</a></span>
+</dt> <dt><code class="code">-mabi=o64</code></dt> <dt><code class="code">-mabi=n32</code></dt> <dt><code class="code">-mabi=64</code></dt> <dt><code class="code">-mabi=eabi</code></dt> <dd>
+<p>Generate code for the given ABI. </p> <p>Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use <samp class="option">-mgp32</samp> to get 32-bit code instead. </p> <p>For information about the O64 ABI, see <a class="uref" href="https://gcc.gnu.org/projects/mipso64-abi.html">https://gcc.gnu.org/projects/mipso64-abi.html</a>. </p> <p>GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with <samp class="option">-mabi=32</samp> <samp class="option">-mfp64</samp>. This ABI relies on the <code class="code">mthc1</code> and <code class="code">mfhc1</code> instructions and is therefore only supported for MIPS32R2, MIPS32R3 and MIPS32R5 processors. </p> <p>The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in ‘<samp class="samp">$f0</samp>’ only, not a ‘<samp class="samp">$f0</samp>’/‘<samp class="samp">$f1</samp>’ pair. The set of call-saved registers also remains the same in that the even-numbered double-precision registers are saved. </p> <p>Two additional variants of the o32 ABI are supported to enable a transition from 32-bit to 64-bit registers. These are FPXX (<samp class="option">-mfpxx</samp>) and FP64A (<samp class="option">-mfp64</samp> <samp class="option">-mno-odd-spreg</samp>). The FPXX extension mandates that all code must execute correctly when run using 32-bit or 64-bit registers. The code can be interlinked with either FP32 or FP64, but not both. The FP64A extension is similar to the FP64 extension but forbids the use of odd-numbered single-precision registers. This can be used in conjunction with the <code class="code">FRE</code> mode of FPUs in MIPS32R5 processors and allows both FP32 and FP64A code to interlink and run in the same process without changing FPU modes. </p> </dd> <dt>
+ <span><code class="code">-mabicalls</code><a class="copiable-link" href="#index-mabicalls"> ¶</a></span>
+</dt> <dt><code class="code">-mno-abicalls</code></dt> <dd>
+<p>Generate (do not generate) code that is suitable for SVR4-style dynamic objects. <samp class="option">-mabicalls</samp> is the default for SVR4-based systems. </p> </dd> <dt><code class="code">-mshared</code></dt> <dt><code class="code">-mno-shared</code></dt> <dd>
+<p>Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries. This option only affects <samp class="option">-mabicalls</samp>. </p> <p>All <samp class="option">-mabicalls</samp> code has traditionally been position-independent, regardless of options like <samp class="option">-fPIC</samp> and <samp class="option">-fpic</samp>. However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by <samp class="option">-mno-shared</samp>. </p> <p><samp class="option">-mno-shared</samp> depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using <samp class="option">-mno-shared</samp> generally makes executables both smaller and quicker. </p> <p><samp class="option">-mshared</samp> is the default. </p> </dd> <dt>
+ <span><code class="code">-mplt</code><a class="copiable-link" href="#index-mplt"> ¶</a></span>
+</dt> <dt><code class="code">-mno-plt</code></dt> <dd>
+<p>Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects <samp class="option">-mno-shared -mabicalls</samp>. For the n64 ABI, this option has no effect without <samp class="option">-msym32</samp>. </p> <p>You can make <samp class="option">-mplt</samp> the default by configuring GCC with <samp class="option">--with-mips-plt</samp>. The default is <samp class="option">-mno-plt</samp> otherwise. </p> </dd> <dt>
+ <span><code class="code">-mxgot</code><a class="copiable-link" href="#index-mxgot-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-xgot</code></dt> <dd>
+<p>Lift (do not lift) the usual restrictions on the size of the global offset table. </p> <p>GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as: </p>  <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">relocation truncated to fit: R_MIPS_GOT16 foobar</pre>
+</div> <p>If this happens, you should recompile your code with <samp class="option">-mxgot</samp>. This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol. </p> <p>Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use <samp class="option">-mxgot</samp> when a single object file accesses more than 64k’s worth of GOT entries. Very few do. </p> <p>These options have no effect unless GCC is generating position independent code. </p> </dd> <dt>
+<span><code class="code">-mgp32</code><a class="copiable-link" href="#index-mgp32"> ¶</a></span>
+</dt> <dd>
+<p>Assume that general-purpose registers are 32 bits wide. </p> </dd> <dt>
+<span><code class="code">-mgp64</code><a class="copiable-link" href="#index-mgp64"> ¶</a></span>
+</dt> <dd>
+<p>Assume that general-purpose registers are 64 bits wide. </p> </dd> <dt>
+<span><code class="code">-mfp32</code><a class="copiable-link" href="#index-mfp32"> ¶</a></span>
+</dt> <dd>
+<p>Assume that floating-point registers are 32 bits wide. </p> </dd> <dt>
+<span><code class="code">-mfp64</code><a class="copiable-link" href="#index-mfp64"> ¶</a></span>
+</dt> <dd>
+<p>Assume that floating-point registers are 64 bits wide. </p> </dd> <dt>
+<span><code class="code">-mfpxx</code><a class="copiable-link" href="#index-mfpxx"> ¶</a></span>
+</dt> <dd>
+<p>Do not assume the width of floating-point registers. </p> </dd> <dt>
+<span><code class="code">-mhard-float</code><a class="copiable-link" href="#index-mhard-float-4"> ¶</a></span>
+</dt> <dd>
+<p>Use floating-point coprocessor instructions. </p> </dd> <dt>
+<span><code class="code">-msoft-float</code><a class="copiable-link" href="#index-msoft-float-8"> ¶</a></span>
+</dt> <dd>
+<p>Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead. </p> </dd> <dt>
+<span><code class="code">-mno-float</code><a class="copiable-link" href="#index-mno-float"> ¶</a></span>
+</dt> <dd>
+<p>Equivalent to <samp class="option">-msoft-float</samp>, but additionally asserts that the program being compiled does not perform any floating-point operations. This option is presently supported only by some bare-metal MIPS configurations, where it may select a special set of libraries that lack all floating-point support (including, for example, the floating-point <code class="code">printf</code> formats). If code compiled with <samp class="option">-mno-float</samp> accidentally contains floating-point operations, it is likely to suffer a link-time or run-time failure. </p> </dd> <dt>
+<span><code class="code">-msingle-float</code><a class="copiable-link" href="#index-msingle-float-1"> ¶</a></span>
+</dt> <dd>
+<p>Assume that the floating-point coprocessor only supports single-precision operations. </p> </dd> <dt>
+<span><code class="code">-mdouble-float</code><a class="copiable-link" href="#index-mdouble-float-2"> ¶</a></span>
+</dt> <dd>
+<p>Assume that the floating-point coprocessor supports double-precision operations. This is the default. </p> </dd> <dt>
+ <span><code class="code">-modd-spreg</code><a class="copiable-link" href="#index-modd-spreg"> ¶</a></span>
+</dt> <dt><code class="code">-mno-odd-spreg</code></dt> <dd>
+<p>Enable the use of odd-numbered single-precision floating-point registers for the o32 ABI. This is the default for processors that are known to support these registers. When using the o32 FPXX ABI, <samp class="option">-mno-odd-spreg</samp> is set by default. </p> </dd> <dt>
+ <span><code class="code">-mabs=2008</code><a class="copiable-link" href="#index-mabs_003d2008"> ¶</a></span>
+</dt> <dt><code class="code">-mabs=legacy</code></dt> <dd>
+<p>These options control the treatment of the special not-a-number (NaN) IEEE 754 floating-point data with the <code class="code">abs.<i class="i">fmt</i></code> and <code class="code">neg.<i class="i">fmt</i></code> machine instructions. </p> <p>By default or when <samp class="option">-mabs=legacy</samp> is used the legacy treatment is selected. In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN. A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is used instead unless the <samp class="option">-ffinite-math-only</samp> option has also been specified. </p> <p>The <samp class="option">-mabs=2008</samp> option selects the IEEE 754-2008 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used for the respective operations. </p> </dd> <dt>
+ <span><code class="code">-mnan=2008</code><a class="copiable-link" href="#index-mnan_003d2008"> ¶</a></span>
+</dt> <dt><code class="code">-mnan=legacy</code></dt> <dd>
+<p>These options control the encoding of the special not-a-number (NaN) IEEE 754 floating-point data. </p> <p>The <samp class="option">-mnan=legacy</samp> option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signaling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1. </p> <p>The <samp class="option">-mnan=2008</samp> option selects the IEEE 754-2008 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0. </p> <p>The default is <samp class="option">-mnan=legacy</samp> unless GCC has been configured with <samp class="option">--with-nan=2008</samp>. </p> </dd> <dt>
+ <span><code class="code">-mllsc</code><a class="copiable-link" href="#index-mllsc"> ¶</a></span>
+</dt> <dt><code class="code">-mno-llsc</code></dt> <dd>
+<p>Use (do not use) ‘<samp class="samp">ll</samp>’, ‘<samp class="samp">sc</samp>’, and ‘<samp class="samp">sync</samp>’ instructions to implement atomic memory built-in functions. When neither option is specified, GCC uses the instructions if the target architecture supports them. </p> <p><samp class="option">-mllsc</samp> is useful if the runtime environment can emulate the instructions and <samp class="option">-mno-llsc</samp> can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with <samp class="option">--with-llsc</samp> and <samp class="option">--without-llsc</samp> respectively. <samp class="option">--with-llsc</samp> is the default for some configurations; see the installation documentation for details. </p> </dd> <dt>
+ <span><code class="code">-mdsp</code><a class="copiable-link" href="#index-mdsp-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-dsp</code></dt> <dd>
+<p>Use (do not use) revision 1 of the MIPS DSP ASE. See <a class="xref" href="mips-dsp-built-in-functions">MIPS DSP Built-in Functions</a>. This option defines the preprocessor macro <code class="code">__mips_dsp</code>. It also defines <code class="code">__mips_dsp_rev</code> to 1. </p> </dd> <dt>
+ <span><code class="code">-mdspr2</code><a class="copiable-link" href="#index-mdspr2"> ¶</a></span>
+</dt> <dt><code class="code">-mno-dspr2</code></dt> <dd>
+<p>Use (do not use) revision 2 of the MIPS DSP ASE. See <a class="xref" href="mips-dsp-built-in-functions">MIPS DSP Built-in Functions</a>. This option defines the preprocessor macros <code class="code">__mips_dsp</code> and <code class="code">__mips_dspr2</code>. It also defines <code class="code">__mips_dsp_rev</code> to 2. </p> </dd> <dt>
+ <span><code class="code">-msmartmips</code><a class="copiable-link" href="#index-msmartmips"> ¶</a></span>
+</dt> <dt><code class="code">-mno-smartmips</code></dt> <dd>
+<p>Use (do not use) the MIPS SmartMIPS ASE. </p> </dd> <dt>
+ <span><code class="code">-mpaired-single</code><a class="copiable-link" href="#index-mpaired-single"> ¶</a></span>
+</dt> <dt><code class="code">-mno-paired-single</code></dt> <dd>
+<p>Use (do not use) paired-single floating-point instructions. See <a class="xref" href="mips-paired-single-support">MIPS Paired-Single Support</a>. This option requires hardware floating-point support to be enabled. </p> </dd> <dt>
+ <span><code class="code">-mdmx</code><a class="copiable-link" href="#index-mdmx"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mdmx</code></dt> <dd>
+<p>Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled. </p> </dd> <dt>
+ <span><code class="code">-mips3d</code><a class="copiable-link" href="#index-mips3d"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mips3d</code></dt> <dd>
+<p>Use (do not use) the MIPS-3D ASE. See <a class="xref" href="mips-3d-built-in-functions">MIPS-3D Built-in Functions</a>. The option <samp class="option">-mips3d</samp> implies <samp class="option">-mpaired-single</samp>. </p> </dd> <dt>
+ <span><code class="code">-mmicromips</code><a class="copiable-link" href="#index-mmicromips"> ¶</a></span>
+</dt> <dt><code class="code">-mno-micromips</code></dt> <dd>
+<p>Generate (do not generate) microMIPS code. </p> <p>MicroMIPS code generation can also be controlled on a per-function basis by means of <code class="code">micromips</code> and <code class="code">nomicromips</code> attributes. See <a class="xref" href="function-attributes">Declaring Attributes of Functions</a>, for more information. </p> </dd> <dt>
+ <span><code class="code">-mmt</code><a class="copiable-link" href="#index-mmt"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mt</code></dt> <dd>
+<p>Use (do not use) MT Multithreading instructions. </p> </dd> <dt>
+ <span><code class="code">-mmcu</code><a class="copiable-link" href="#index-mmcu-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mcu</code></dt> <dd>
+<p>Use (do not use) the MIPS MCU ASE instructions. </p> </dd> <dt>
+ <span><code class="code">-meva</code><a class="copiable-link" href="#index-meva"> ¶</a></span>
+</dt> <dt><code class="code">-mno-eva</code></dt> <dd>
+<p>Use (do not use) the MIPS Enhanced Virtual Addressing instructions. </p> </dd> <dt>
+ <span><code class="code">-mvirt</code><a class="copiable-link" href="#index-mvirt"> ¶</a></span>
+</dt> <dt><code class="code">-mno-virt</code></dt> <dd>
+<p>Use (do not use) the MIPS Virtualization (VZ) instructions. </p> </dd> <dt>
+ <span><code class="code">-mxpa</code><a class="copiable-link" href="#index-mxpa"> ¶</a></span>
+</dt> <dt><code class="code">-mno-xpa</code></dt> <dd>
+<p>Use (do not use) the MIPS eXtended Physical Address (XPA) instructions. </p> </dd> <dt>
+ <span><code class="code">-mcrc</code><a class="copiable-link" href="#index-mcrc"> ¶</a></span>
+</dt> <dt><code class="code">-mno-crc</code></dt> <dd>
+<p>Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions. </p> </dd> <dt>
+ <span><code class="code">-mginv</code><a class="copiable-link" href="#index-mginv"> ¶</a></span>
+</dt> <dt><code class="code">-mno-ginv</code></dt> <dd>
+<p>Use (do not use) the MIPS Global INValidate (GINV) instructions. </p> </dd> <dt>
+ <span><code class="code">-mloongson-mmi</code><a class="copiable-link" href="#index-mloongson-mmi"> ¶</a></span>
+</dt> <dt><code class="code">-mno-loongson-mmi</code></dt> <dd>
+<p>Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). </p> </dd> <dt>
+ <span><code class="code">-mloongson-ext</code><a class="copiable-link" href="#index-mloongson-ext"> ¶</a></span>
+</dt> <dt><code class="code">-mno-loongson-ext</code></dt> <dd>
+<p>Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. </p> </dd> <dt>
+ <span><code class="code">-mloongson-ext2</code><a class="copiable-link" href="#index-mloongson-ext2"> ¶</a></span>
+</dt> <dt><code class="code">-mno-loongson-ext2</code></dt> <dd>
+<p>Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. </p> </dd> <dt>
+<span><code class="code">-mlong64</code><a class="copiable-link" href="#index-mlong64"> ¶</a></span>
+</dt> <dd>
+<p>Force <code class="code">long</code> types to be 64 bits wide. See <samp class="option">-mlong32</samp> for an explanation of the default and the way that the pointer size is determined. </p> </dd> <dt>
+<span><code class="code">-mlong32</code><a class="copiable-link" href="#index-mlong32"> ¶</a></span>
+</dt> <dd>
+<p>Force <code class="code">long</code>, <code class="code">int</code>, and pointer types to be 32 bits wide. </p> <p>The default size of <code class="code">int</code>s, <code class="code">long</code>s and pointers depends on the ABI. All the supported ABIs use 32-bit <code class="code">int</code>s. The n64 ABI uses 64-bit <code class="code">long</code>s, as does the 64-bit EABI; the others use 32-bit <code class="code">long</code>s. Pointers are the same size as <code class="code">long</code>s, or the same size as integer registers, whichever is smaller. </p> </dd> <dt>
+ <span><code class="code">-msym32</code><a class="copiable-link" href="#index-msym32"> ¶</a></span>
+</dt> <dt><code class="code">-mno-sym32</code></dt> <dd>
+<p>Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with <samp class="option">-mabi=64</samp> and <samp class="option">-mno-abicalls</samp> because it allows GCC to generate shorter and faster references to symbolic addresses. </p> </dd> <dt>
+<span><code class="code">-G <var class="var">num</var></code><a class="copiable-link" href="#index-G-2"> ¶</a></span>
+</dt> <dd>
+<p>Put definitions of externally-visible data in a small data section if that data is no bigger than <var class="var">num</var> bytes. GCC can then generate more efficient accesses to the data; see <samp class="option">-mgpopt</samp> for details. </p> <p>The default <samp class="option">-G</samp> option depends on the configuration. </p> </dd> <dt>
+ <span><code class="code">-mlocal-sdata</code><a class="copiable-link" href="#index-mlocal-sdata"> ¶</a></span>
+</dt> <dt><code class="code">-mno-local-sdata</code></dt> <dd>
+<p>Extend (do not extend) the <samp class="option">-G</samp> behavior to local data too, such as to static variables in C. <samp class="option">-mlocal-sdata</samp> is the default for all configurations. </p> <p>If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with <samp class="option">-mno-local-sdata</samp>. You might also want to build large libraries with <samp class="option">-mno-local-sdata</samp>, so that the libraries leave more room for the main program. </p> </dd> <dt>
+ <span><code class="code">-mextern-sdata</code><a class="copiable-link" href="#index-mextern-sdata"> ¶</a></span>
+</dt> <dt><code class="code">-mno-extern-sdata</code></dt> <dd>
+<p>Assume (do not assume) that externally-defined data is in a small data section if the size of that data is within the <samp class="option">-G</samp> limit. <samp class="option">-mextern-sdata</samp> is the default for all configurations. </p> <p>If you compile a module <var class="var">Mod</var> with <samp class="option">-mextern-sdata</samp> <samp class="option">-G <var class="var">num</var></samp> <samp class="option">-mgpopt</samp>, and <var class="var">Mod</var> references a variable <var class="var">Var</var> that is no bigger than <var class="var">num</var> bytes, you must make sure that <var class="var">Var</var> is placed in a small data section. If <var class="var">Var</var> is defined by another module, you must either compile that module with a high-enough <samp class="option">-G</samp> setting or attach a <code class="code">section</code> attribute to <var class="var">Var</var>’s definition. If <var class="var">Var</var> is common, you must link the application with a high-enough <samp class="option">-G</samp> setting. </p> <p>The easiest way of satisfying these restrictions is to compile and link every module with the same <samp class="option">-G</samp> option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported <samp class="option">-G</samp> setting and additionally using <samp class="option">-mno-extern-sdata</samp> to stop the library from making assumptions about externally-defined data. </p> </dd> <dt>
+ <span><code class="code">-mgpopt</code><a class="copiable-link" href="#index-mgpopt"> ¶</a></span>
+</dt> <dt><code class="code">-mno-gpopt</code></dt> <dd>
+<p>Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see <samp class="option">-G</samp>, <samp class="option">-mlocal-sdata</samp> and <samp class="option">-mextern-sdata</samp>. <samp class="option">-mgpopt</samp> is the default for all configurations. </p> <p><samp class="option">-mno-gpopt</samp> is useful for cases where the <code class="code">$gp</code> register might not hold the value of <code class="code">_gp</code>. For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines pass an unknown value in <code class="code">$gp</code>. (In such situations, the boot monitor itself is usually compiled with <samp class="option">-G0</samp>.) </p> <p><samp class="option">-mno-gpopt</samp> implies <samp class="option">-mno-local-sdata</samp> and <samp class="option">-mno-extern-sdata</samp>. </p> </dd> <dt>
+ <span><code class="code">-membedded-data</code><a class="copiable-link" href="#index-membedded-data"> ¶</a></span>
+</dt> <dt><code class="code">-mno-embedded-data</code></dt> <dd>
+<p>Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems. </p> </dd> <dt>
+ <span><code class="code">-muninit-const-in-rodata</code><a class="copiable-link" href="#index-muninit-const-in-rodata"> ¶</a></span>
+</dt> <dt><code class="code">-mno-uninit-const-in-rodata</code></dt> <dd>
+<p>Put uninitialized <code class="code">const</code> variables in the read-only data section. This option is only meaningful in conjunction with <samp class="option">-membedded-data</samp>. </p> </dd> <dt>
+<span><code class="code">-mcode-readable=<var class="var">setting</var></code><a class="copiable-link" href="#index-mcode-readable"> ¶</a></span>
+</dt> <dd>
+<p>Specify whether GCC may generate code that reads from executable sections. There are three possible settings: </p> <dl class="table"> <dt><code class="code">-mcode-readable=yes</code></dt> <dd>
+<p>Instructions may freely access executable sections. This is the default setting. </p> </dd> <dt><code class="code">-mcode-readable=pcrel</code></dt> <dd>
+<p>MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM. </p> </dd> <dt><code class="code">-mcode-readable=no</code></dt> <dd><p>Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM. </p></dd> </dl> </dd> <dt>
+ <span><code class="code">-msplit-addresses</code><a class="copiable-link" href="#index-msplit-addresses"> ¶</a></span>
+</dt> <dt><code class="code">-mno-split-addresses</code></dt> <dd>
+<p>Enable (disable) use of the <code class="code">%hi()</code> and <code class="code">%lo()</code> assembler relocation operators. This option has been superseded by <samp class="option">-mexplicit-relocs</samp> but is retained for backwards compatibility. </p> </dd> <dt>
+ <span><code class="code">-mexplicit-relocs</code><a class="copiable-link" href="#index-mexplicit-relocs-2"> ¶</a></span>
+</dt> <dt><code class="code">-mno-explicit-relocs</code></dt> <dd>
+<p>Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by <samp class="option">-mno-explicit-relocs</samp>, is to use assembler macros instead. </p> <p><samp class="option">-mexplicit-relocs</samp> is the default if GCC was configured to use an assembler that supports relocation operators. </p> </dd> <dt>
+ <span><code class="code">-mcheck-zero-division</code><a class="copiable-link" href="#index-mcheck-zero-division-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-check-zero-division</code></dt> <dd>
+<p>Trap (do not trap) on integer division by zero. </p> <p>The default is <samp class="option">-mcheck-zero-division</samp>. </p> </dd> <dt>
+ <span><code class="code">-mdivide-traps</code><a class="copiable-link" href="#index-mdivide-traps"> ¶</a></span>
+</dt> <dt><code class="code">-mdivide-breaks</code></dt> <dd>
+<p>MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (<code class="code">SIGFPE</code>). Use <samp class="option">-mdivide-traps</samp> to allow conditional traps on architectures that support them and <samp class="option">-mdivide-breaks</samp> to force the use of breaks. </p> <p>The default is usually <samp class="option">-mdivide-traps</samp>, but this can be overridden at configure time using <samp class="option">--with-divide=breaks</samp>. Divide-by-zero checks can be completely disabled using <samp class="option">-mno-check-zero-division</samp>. </p> </dd> <dt>
+ <span><code class="code">-mload-store-pairs</code><a class="copiable-link" href="#index-mload-store-pairs"> ¶</a></span>
+</dt> <dt><code class="code">-mno-load-store-pairs</code></dt> <dd>
+<p>Enable (disable) an optimization that pairs consecutive load or store instructions to enable load/store bonding. This option is enabled by default but only takes effect when the selected architecture is known to support bonding. </p> </dd> <dt>
+ <span><code class="code">-munaligned-access</code><a class="copiable-link" href="#index-munaligned-access-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-unaligned-access</code></dt> <dd>
+<p>Enable (disable) direct unaligned access for MIPS Release 6. MIPSr6 requires load/store unaligned-access support, by hardware or trap&amp;emulate. So <samp class="option">-mno-unaligned-access</samp> may be needed by kernel. </p> </dd> <dt>
+ <span><code class="code">-mmemcpy</code><a class="copiable-link" href="#index-mmemcpy-2"> ¶</a></span>
+</dt> <dt><code class="code">-mno-memcpy</code></dt> <dd>
+<p>Force (do not force) the use of <code class="code">memcpy</code> for non-trivial block moves. The default is <samp class="option">-mno-memcpy</samp>, which allows GCC to inline most constant-sized copies. </p> </dd> <dt>
+ <span><code class="code">-mlong-calls</code><a class="copiable-link" href="#index-mlong-calls-6"> ¶</a></span>
+</dt> <dt><code class="code">-mno-long-calls</code></dt> <dd>
+<p>Disable (do not disable) use of the <code class="code">jal</code> instruction. Calling functions using <code class="code">jal</code> is more efficient but requires the caller and callee to be in the same 256 megabyte segment. </p> <p>This option has no effect on abicalls code. The default is <samp class="option">-mno-long-calls</samp>. </p> </dd> <dt>
+ <span><code class="code">-mmad</code><a class="copiable-link" href="#index-mmad"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mad</code></dt> <dd>
+<p>Enable (disable) use of the <code class="code">mad</code>, <code class="code">madu</code> and <code class="code">mul</code> instructions, as provided by the R4650 ISA. </p> </dd> <dt>
+ <span><code class="code">-mimadd</code><a class="copiable-link" href="#index-mimadd"> ¶</a></span>
+</dt> <dt><code class="code">-mno-imadd</code></dt> <dd>
+<p>Enable (disable) use of the <code class="code">madd</code> and <code class="code">msub</code> integer instructions. The default is <samp class="option">-mimadd</samp> on architectures that support <code class="code">madd</code> and <code class="code">msub</code> except for the 74k architecture where it was found to generate slower code. </p> </dd> <dt>
+ <span><code class="code">-mfused-madd</code><a class="copiable-link" href="#index-mfused-madd-1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fused-madd</code></dt> <dd>
+<p>Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available. The default is <samp class="option">-mfused-madd</samp>. </p> <p>On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions. </p> </dd> <dt>
+<span><code class="code">-nocpp</code><a class="copiable-link" href="#index-nocpp"> ¶</a></span>
+</dt> <dd>
+<p>Tell the MIPS assembler to not run its preprocessor over user assembler files (with a ‘<samp class="samp">.s</samp>’ suffix) when assembling them. </p> </dd> <dt>
+ <span><code class="code">-mfix-24k</code><a class="copiable-link" href="#index-mfix-24k"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-24k</code></dt> <dd>
+<p>Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC. </p> </dd> <dt>
+ <span><code class="code">-mfix-r4000</code><a class="copiable-link" href="#index-mfix-r4000"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-r4000</code></dt> <dd>
+<p>Work around certain R4000 CPU errata: </p>
+<ul class="itemize mark-minus"> <li>A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. </li>
+<li>A double-word or a variable shift may give an incorrect result if executed while an integer multiplication is in progress. </li>
+<li>An integer division may give an incorrect result if started in a delay slot of a taken branch or a jump. </li>
+</ul> </dd> <dt>
+ <span><code class="code">-mfix-r4400</code><a class="copiable-link" href="#index-mfix-r4400"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-r4400</code></dt> <dd>
+<p>Work around certain R4400 CPU errata: </p>
+<ul class="itemize mark-minus"> <li>A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. </li>
+</ul> </dd> <dt>
+ <span><code class="code">-mfix-r10000</code><a class="copiable-link" href="#index-mfix-r10000"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-r10000</code></dt> <dd>
+<p>Work around certain R10000 errata: </p>
+<ul class="itemize mark-minus"> <li>
+<code class="code">ll</code>/<code class="code">sc</code> sequences may not behave atomically on revisions prior to 3.0. They may deadlock on revisions 2.6 and earlier. </li>
+</ul> <p>This option can only be used if the target architecture supports branch-likely instructions. <samp class="option">-mfix-r10000</samp> is the default when <samp class="option">-march=r10000</samp> is used; <samp class="option">-mno-fix-r10000</samp> is the default otherwise. </p> </dd> <dt>
+<span><code class="code">-mfix-r5900</code><a class="copiable-link" href="#index-mfix-r5900"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-r5900</code></dt> <dd>
+<p>Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a <code class="code">nop</code> instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. The workaround is implemented by the assembler rather than by GCC. </p> </dd> <dt>
+<span><code class="code">-mfix-rm7000</code><a class="copiable-link" href="#index-mfix-rm7000"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-rm7000</code></dt> <dd>
+<p>Work around the RM7000 <code class="code">dmult</code>/<code class="code">dmultu</code> errata. The workarounds are implemented by the assembler rather than by GCC. </p> </dd> <dt>
+<span><code class="code">-mfix-vr4120</code><a class="copiable-link" href="#index-mfix-vr4120"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-vr4120</code></dt> <dd>
+<p>Work around certain VR4120 errata: </p>
+<ul class="itemize mark-minus"> <li>
+<code class="code">dmultu</code> does not always produce the correct result. </li>
+<li>
+<code class="code">div</code> and <code class="code">ddiv</code> do not always produce the correct result if one of the operands is negative. </li>
+</ul> <p>The workarounds for the division errata rely on special functions in <samp class="file">libgcc.a</samp>. At present, these functions are only provided by the <code class="code">mips64vr*-elf</code> configurations. </p> <p>Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself. </p> </dd> <dt>
+<span><code class="code">-mfix-vr4130</code><a class="copiable-link" href="#index-mfix-vr4130"> ¶</a></span>
+</dt> <dd>
+<p>Work around the VR4130 <code class="code">mflo</code>/<code class="code">mfhi</code> errata. The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using <code class="code">mflo</code> and <code class="code">mfhi</code> if the VR4130 <code class="code">macc</code>, <code class="code">macchi</code>, <code class="code">dmacc</code> and <code class="code">dmacchi</code> instructions are available instead. </p> </dd> <dt>
+<span><code class="code">-mfix-sb1</code><a class="copiable-link" href="#index-mfix-sb1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fix-sb1</code></dt> <dd>
+<p>Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 “F1” and “F2” floating-point errata.) </p> </dd> <dt>
+<span><code class="code">-mr10k-cache-barrier=<var class="var">setting</var></code><a class="copiable-link" href="#index-mr10k-cache-barrier"> ¶</a></span>
+</dt> <dd>
+<p>Specify whether GCC should insert cache barriers to avoid the side effects of speculation on R10K processors. </p> <p>In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the “taken” branch. It later aborts these instructions if the predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects. </p> <p>This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the “dirty” line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a full description, including other potential problems. </p> <p>One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. <samp class="option">-mr10k-cache-barrier=<var class="var">setting</var></samp> controls GCC’s implementation of this workaround. It assumes that aborted accesses to any byte in the following regions does not have side effects: </p> <ol class="enumerate"> <li> the memory occupied by the current function’s stack frame; </li>
+<li> the memory occupied by an incoming stack argument; </li>
+<li> the memory occupied by an object with a link-time-constant address. </li>
+</ol> <p>It is the kernel’s responsibility to ensure that speculative accesses to these regions are indeed safe. </p> <p>If the input program contains a function declaration such as: </p> <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">void foo (void);</pre>
+</div> <p>then the implementation of <code class="code">foo</code> must allow <code class="code">j foo</code> and <code class="code">jal foo</code> to be executed speculatively. GCC honors this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written assembly code) to do the same. </p> <p>The option has three forms: </p> <dl class="table"> <dt><code class="code">-mr10k-cache-barrier=load-store</code></dt> <dd>
+<p>Insert a cache barrier before a load or store that might be speculatively executed and that might have side effects even if aborted. </p> </dd> <dt><code class="code">-mr10k-cache-barrier=store</code></dt> <dd>
+<p>Insert a cache barrier before a store that might be speculatively executed and that might have side effects even if aborted. </p> </dd> <dt><code class="code">-mr10k-cache-barrier=none</code></dt> <dd><p>Disable the insertion of cache barriers. This is the default setting. </p></dd> </dl> </dd> <dt>
+<span><code class="code">-mflush-func=<var class="var">func</var></code><a class="copiable-link" href="#index-mflush-func"> ¶</a></span>
+</dt> <dt><code class="code">-mno-flush-func</code></dt> <dd>
+<p>Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common <code class="code">_flush_func</code>, that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either <code class="code">_flush_func</code> or <code class="code">__cpu_flush</code>. </p> </dd> <dt>
+<span><code class="code">mbranch-cost=<var class="var">num</var></code><a class="copiable-link" href="#index-mbranch-cost-3"> ¶</a></span>
+</dt> <dd>
+<p>Set the cost of branches to roughly <var class="var">num</var> “simple” instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the <samp class="option">-mtune</samp> setting. </p> </dd> <dt>
+ <span><code class="code">-mbranch-likely</code><a class="copiable-link" href="#index-mbranch-likely"> ¶</a></span>
+</dt> <dt><code class="code">-mno-branch-likely</code></dt> <dd>
+<p>Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors that implement those architectures; for those, Branch Likely instructions are not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use. </p> </dd> <dt>
+  <span><code class="code">-mcompact-branches=never</code><a class="copiable-link" href="#index-mcompact-branches_003dnever"> ¶</a></span>
+</dt> <dt><code class="code">-mcompact-branches=optimal</code></dt> <dt><code class="code">-mcompact-branches=always</code></dt> <dd>
+<p>These options control which form of branches will be generated. The default is <samp class="option">-mcompact-branches=optimal</samp>. </p> <p>The <samp class="option">-mcompact-branches=never</samp> option ensures that compact branch instructions will never be generated. </p> <p>The <samp class="option">-mcompact-branches=always</samp> option ensures that a compact branch instruction will be generated if available for MIPS Release 6 onwards. If a compact branch instruction is not available (or pre-R6), a delay slot form of the branch will be used instead. </p> <p>If it is used for MIPS16/microMIPS targets, it will be just ignored now. The behaviour for MIPS16/microMIPS may change in future, since they do have some compact branch instructions. </p> <p>The <samp class="option">-mcompact-branches=optimal</samp> option will cause a delay slot branch to be used if one is available in the current ISA and the delay slot is successfully filled. If the delay slot is not filled, a compact branch will be chosen if one is available. </p> </dd> <dt>
+<span><code class="code">-mfp-exceptions</code><a class="copiable-link" href="#index-mfp-exceptions"> ¶</a></span>
+</dt> <dt><code class="code">-mno-fp-exceptions</code></dt> <dd>
+<p>Specifies whether FP exceptions are enabled. This affects how FP instructions are scheduled for some processors. The default is that FP exceptions are enabled. </p> <p>For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe. </p> </dd> <dt>
+<span><code class="code">-mvr4130-align</code><a class="copiable-link" href="#index-mvr4130-align"> ¶</a></span>
+</dt> <dt><code class="code">-mno-vr4130-align</code></dt> <dd>
+<p>The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC aligns pairs of instructions that it thinks should execute in parallel. </p> <p>This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level <samp class="option">-O3</samp>. </p> </dd> <dt>
+<span><code class="code">-msynci</code><a class="copiable-link" href="#index-msynci"> ¶</a></span>
+</dt> <dt><code class="code">-mno-synci</code></dt> <dd>
+<p>Enable (disable) generation of <code class="code">synci</code> instructions on architectures that support it. The <code class="code">synci</code> instructions (if enabled) are generated when <code class="code">__builtin___clear_cache</code> is compiled. </p> <p>This option defaults to <samp class="option">-mno-synci</samp>, but the default can be overridden by configuring GCC with <samp class="option">--with-synci</samp>. </p> <p>When compiling code for single processor systems, it is generally safe to use <code class="code">synci</code>. However, on many multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to undefined behavior. </p> </dd> <dt>
+<span><code class="code">-mrelax-pic-calls</code><a class="copiable-link" href="#index-mrelax-pic-calls"> ¶</a></span>
+</dt> <dt><code class="code">-mno-relax-pic-calls</code></dt> <dd>
+<p>Try to turn PIC calls that are normally dispatched via register <code class="code">$25</code> into direct calls. This is only possible if the linker can resolve the destination at link time and if the destination is within range for a direct call. </p> <p><samp class="option">-mrelax-pic-calls</samp> is the default if GCC was configured to use an assembler and a linker that support the <code class="code">.reloc</code> assembly directive and <samp class="option">-mexplicit-relocs</samp> is in effect. With <samp class="option">-mno-explicit-relocs</samp>, this optimization can be performed by the assembler and the linker alone without help from the compiler. </p> </dd> <dt>
+ <span><code class="code">-mmcount-ra-address</code><a class="copiable-link" href="#index-mmcount-ra-address"> ¶</a></span>
+</dt> <dt><code class="code">-mno-mcount-ra-address</code></dt> <dd>
+<p>Emit (do not emit) code that allows <code class="code">_mcount</code> to modify the calling function’s return address. When enabled, this option extends the usual <code class="code">_mcount</code> interface with a new <var class="var">ra-address</var> parameter, which has type <code class="code">intptr_t *</code> and is passed in register <code class="code">$12</code>. <code class="code">_mcount</code> can then modify the return address by doing both of the following: </p>
+<ul class="itemize mark-bullet"> <li>Returning the new address in register <code class="code">$31</code>. </li>
+<li>Storing the new address in <code class="code">*<var class="var">ra-address</var></code>, if <var class="var">ra-address</var> is nonnull. </li>
+</ul> <p>The default is <samp class="option">-mno-mcount-ra-address</samp>. </p> </dd> <dt>
+<span><code class="code">-mframe-header-opt</code><a class="copiable-link" href="#index-mframe-header-opt"> ¶</a></span>
+</dt> <dt><code class="code">-mno-frame-header-opt</code></dt> <dd>
+<p>Enable (disable) frame header optimization in the o32 ABI. When using the o32 ABI, calling functions will allocate 16 bytes on the stack for the called function to write out register arguments. When enabled, this optimization will suppress the allocation of the frame header if it can be determined that it is unused. </p> <p>This optimization is off by default at all optimization levels. </p> </dd> <dt>
+<span><code class="code">-mlxc1-sxc1</code><a class="copiable-link" href="#index-mlxc1-sxc1"> ¶</a></span>
+</dt> <dt><code class="code">-mno-lxc1-sxc1</code></dt> <dd>
+<p>When applicable, enable (disable) the generation of <code class="code">lwxc1</code>, <code class="code">swxc1</code>, <code class="code">ldxc1</code>, <code class="code">sdxc1</code> instructions. Enabled by default. </p> </dd> <dt>
+<span><code class="code">-mmadd4</code><a class="copiable-link" href="#index-mmadd4"> ¶</a></span>
+</dt> <dt><code class="code">-mno-madd4</code></dt> <dd>
+<p>When applicable, enable (disable) the generation of 4-operand <code class="code">madd.s</code>, <code class="code">madd.d</code> and related instructions. Enabled by default. </p> </dd> </dl> </div>  <div class="nav-panel"> <p> Next: <a href="mmix-options">MMIX Options</a>, Previous: <a href="microblaze-options">MicroBlaze Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
+  <p class="_attribution-p">
+    &copy; Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
+    <a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/MIPS-Options.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/MIPS-Options.html</a>
+  </p>
+</div>