diff options
Diffstat (limited to 'devdocs/gcc~13/rs_002f6000-and-powerpc-options.html')
| -rw-r--r-- | devdocs/gcc~13/rs_002f6000-and-powerpc-options.html | 335 |
1 files changed, 335 insertions, 0 deletions
diff --git a/devdocs/gcc~13/rs_002f6000-and-powerpc-options.html b/devdocs/gcc~13/rs_002f6000-and-powerpc-options.html new file mode 100644 index 00000000..ad627ca4 --- /dev/null +++ b/devdocs/gcc~13/rs_002f6000-and-powerpc-options.html @@ -0,0 +1,335 @@ +<div class="subsection-level-extent" id="RS_002f6000-and-PowerPC-Options"> <div class="nav-panel"> <p> Next: <a href="rx-options" accesskey="n" rel="next">RX Options</a>, Previous: <a href="rl78-options" accesskey="p" rel="prev">RL78 Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div> <h1 class="subsection" id="IBM-RS_002f6000-and-PowerPC-Options"><span>3.19.42 IBM RS/6000 and PowerPC Options<a class="copiable-link" href="#IBM-RS_002f6000-and-PowerPC-Options"> ¶</a></span></h1> <p>These ‘<samp class="samp">-m</samp>’ options are defined for the IBM RS/6000 and PowerPC: </p> +<dl class="table"> <dt> +<span><code class="code">-mpowerpc-gpopt</code><a class="copiable-link" href="#index-mpowerpc-gpopt"> ¶</a></span> +</dt> <dt><code class="code">-mno-powerpc-gpopt</code></dt> <dt><code class="code">-mpowerpc-gfxopt</code></dt> <dt><code class="code">-mno-powerpc-gfxopt</code></dt> <dt><code class="code">-mpowerpc64</code></dt> <dt><code class="code">-mno-powerpc64</code></dt> <dt><code class="code">-mmfcrf</code></dt> <dt><code class="code">-mno-mfcrf</code></dt> <dt><code class="code">-mpopcntb</code></dt> <dt><code class="code">-mno-popcntb</code></dt> <dt><code class="code">-mpopcntd</code></dt> <dt><code class="code">-mno-popcntd</code></dt> <dt><code class="code">-mfprnd</code></dt> <dt><code class="code">-mno-fprnd</code></dt> <dt><code class="code">-mcmpb</code></dt> <dt><code class="code">-mno-cmpb</code></dt> <dt><code class="code">-mhard-dfp</code></dt> <dt><code class="code">-mno-hard-dfp</code></dt> <dd> +<p>You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC. Specifying the <samp class="option">-mcpu=<var class="var">cpu_type</var></samp> overrides the specification of these options. We recommend you use the <samp class="option">-mcpu=<var class="var">cpu_type</var></samp> option rather than the options listed above. </p> <p>Specifying <samp class="option">-mpowerpc-gpopt</samp> allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying <samp class="option">-mpowerpc-gfxopt</samp> allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select. </p> <p>The <samp class="option">-mmfcrf</samp> option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The <samp class="option">-mpopcntb</samp> option allows GCC to generate the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The <samp class="option">-mpopcntd</samp> option allows GCC to generate the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture. The <samp class="option">-mfprnd</samp> option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The <samp class="option">-mcmpb</samp> option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The <samp class="option">-mhard-dfp</samp> option allows GCC to generate the decimal floating-point instructions implemented on some POWER processors. </p> <p>The <samp class="option">-mpowerpc64</samp> option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to <samp class="option">-mno-powerpc64</samp>. </p> </dd> <dt> +<span><code class="code">-mcpu=<var class="var">cpu_type</var></code><a class="copiable-link" href="#index-mcpu-10"> ¶</a></span> +</dt> <dd> +<p>Set architecture type, register usage, and instruction scheduling parameters for machine type <var class="var">cpu_type</var>. Supported values for <var class="var">cpu_type</var> are ‘<samp class="samp">401</samp>’, ‘<samp class="samp">403</samp>’, ‘<samp class="samp">405</samp>’, ‘<samp class="samp">405fp</samp>’, ‘<samp class="samp">440</samp>’, ‘<samp class="samp">440fp</samp>’, ‘<samp class="samp">464</samp>’, ‘<samp class="samp">464fp</samp>’, ‘<samp class="samp">476</samp>’, ‘<samp class="samp">476fp</samp>’, ‘<samp class="samp">505</samp>’, ‘<samp class="samp">601</samp>’, ‘<samp class="samp">602</samp>’, ‘<samp class="samp">603</samp>’, ‘<samp class="samp">603e</samp>’, ‘<samp class="samp">604</samp>’, ‘<samp class="samp">604e</samp>’, ‘<samp class="samp">620</samp>’, ‘<samp class="samp">630</samp>’, ‘<samp class="samp">740</samp>’, ‘<samp class="samp">7400</samp>’, ‘<samp class="samp">7450</samp>’, ‘<samp class="samp">750</samp>’, ‘<samp class="samp">801</samp>’, ‘<samp class="samp">821</samp>’, ‘<samp class="samp">823</samp>’, ‘<samp class="samp">860</samp>’, ‘<samp class="samp">970</samp>’, ‘<samp class="samp">8540</samp>’, ‘<samp class="samp">a2</samp>’, ‘<samp class="samp">e300c2</samp>’, ‘<samp class="samp">e300c3</samp>’, ‘<samp class="samp">e500mc</samp>’, ‘<samp class="samp">e500mc64</samp>’, ‘<samp class="samp">e5500</samp>’, ‘<samp class="samp">e6500</samp>’, ‘<samp class="samp">ec603e</samp>’, ‘<samp class="samp">G3</samp>’, ‘<samp class="samp">G4</samp>’, ‘<samp class="samp">G5</samp>’, ‘<samp class="samp">titan</samp>’, ‘<samp class="samp">power3</samp>’, ‘<samp class="samp">power4</samp>’, ‘<samp class="samp">power5</samp>’, ‘<samp class="samp">power5+</samp>’, ‘<samp class="samp">power6</samp>’, ‘<samp class="samp">power6x</samp>’, ‘<samp class="samp">power7</samp>’, ‘<samp class="samp">power8</samp>’, ‘<samp class="samp">power9</samp>’, ‘<samp class="samp">power10</samp>’, ‘<samp class="samp">powerpc</samp>’, ‘<samp class="samp">powerpc64</samp>’, ‘<samp class="samp">powerpc64le</samp>’, ‘<samp class="samp">rs64</samp>’, and ‘<samp class="samp">native</samp>’. </p> <p><samp class="option">-mcpu=powerpc</samp>, <samp class="option">-mcpu=powerpc64</samp>, and <samp class="option">-mcpu=powerpc64le</samp> specify pure 32-bit PowerPC (either endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes. </p> <p>Specifying ‘<samp class="samp">native</samp>’ as cpu type detects and selects the architecture option that corresponds to the host processor of the system performing the compilation. <samp class="option">-mcpu=native</samp> has no effect if GCC does not recognize the processor. </p> <p>The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on others. </p> <p>The <samp class="option">-mcpu</samp> options automatically enable or disable the following options: </p> <div class="example smallexample"> <pre class="example-preformatted" data-language="cpp">-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple +-mpopcntb -mpopcntd -mpowerpc64 +-mpowerpc-gpopt -mpowerpc-gfxopt +-mmulhw -mdlmzb -mmfpgpr -mvsx +-mcrypto -mhtm -mpower8-fusion -mpower8-vector +-mquad-memory -mquad-memory-atomic -mfloat128 +-mfloat128-hardware -mprefixed -mpcrel -mmma +-mrop-protect</pre> +</div> <p>The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn’t necessarily reflect the actual hardware’s capabilities. If you wish to set an individual option to a particular value, you may specify it after the <samp class="option">-mcpu</samp> option, like <samp class="option">-mcpu=970 -mno-altivec</samp>. </p> <p>On AIX, the <samp class="option">-maltivec</samp> and <samp class="option">-mpowerpc64</samp> options are not enabled or disabled by the <samp class="option">-mcpu</samp> option at present because AIX does not have full support for these options. You may still enable or disable them individually if you’re sure it’ll work in your environment. </p> </dd> <dt> +<span><code class="code">-mtune=<var class="var">cpu_type</var></code><a class="copiable-link" href="#index-mtune-13"> ¶</a></span> +</dt> <dd> +<p>Set the instruction scheduling parameters for machine type <var class="var">cpu_type</var>, but do not set the architecture type or register usage, as <samp class="option">-mcpu=<var class="var">cpu_type</var></samp> does. The same values for <var class="var">cpu_type</var> are used for <samp class="option">-mtune</samp> as for <samp class="option">-mcpu</samp>. If both are specified, the code generated uses the architecture and registers set by <samp class="option">-mcpu</samp>, but the scheduling parameters set by <samp class="option">-mtune</samp>. </p> </dd> <dt> +<span><code class="code">-mcmodel=small</code><a class="copiable-link" href="#index-mcmodel_003dsmall-2"> ¶</a></span> +</dt> <dd> +<p>Generate PowerPC64 code for the small model: The TOC is limited to 64k. </p> </dd> <dt> +<span><code class="code">-mcmodel=medium</code><a class="copiable-link" href="#index-mcmodel_003dmedium"> ¶</a></span> +</dt> <dd> +<p>Generate PowerPC64 code for the medium model: The TOC and other static data may be up to a total of 4G in size. This is the default for 64-bit Linux. </p> </dd> <dt> +<span><code class="code">-mcmodel=large</code><a class="copiable-link" href="#index-mcmodel_003dlarge-2"> ¶</a></span> +</dt> <dd> +<p>Generate PowerPC64 code for the large model: The TOC may be up to 4G in size. Other data and code is only limited by the 64-bit address space. </p> </dd> <dt> + <span><code class="code">-maltivec</code><a class="copiable-link" href="#index-maltivec"> ¶</a></span> +</dt> <dt><code class="code">-mno-altivec</code></dt> <dd> +<p>Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set <samp class="option">-mabi=altivec</samp> to adjust the current ABI with AltiVec ABI enhancements. </p> <p>When <samp class="option">-maltivec</samp> is used, the element order for AltiVec intrinsics such as <code class="code">vec_splat</code>, <code class="code">vec_extract</code>, and <code class="code">vec_insert</code> match array element order corresponding to the endianness of the target. That is, element zero identifies the leftmost element in a vector register when targeting a big-endian platform, and identifies the rightmost element in a vector register when targeting a little-endian platform. </p> </dd> <dt> + <span><code class="code">-mvrsave</code><a class="copiable-link" href="#index-mvrsave"> ¶</a></span> +</dt> <dt><code class="code">-mno-vrsave</code></dt> <dd> +<p>Generate VRSAVE instructions when generating AltiVec code. </p> </dd> <dt> +<span><code class="code">-msecure-plt</code><a class="copiable-link" href="#index-msecure-plt"> ¶</a></span> +</dt> <dd> +<p>Generate code that allows <code class="command">ld</code> and <code class="command">ld.so</code> to build executables and shared libraries with non-executable <code class="code">.plt</code> and <code class="code">.got</code> sections. This is a PowerPC 32-bit SYSV ABI option. </p> </dd> <dt> +<span><code class="code">-mbss-plt</code><a class="copiable-link" href="#index-mbss-plt"> ¶</a></span> +</dt> <dd> +<p>Generate code that uses a BSS <code class="code">.plt</code> section that <code class="command">ld.so</code> fills in, and requires <code class="code">.plt</code> and <code class="code">.got</code> sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option. </p> </dd> <dt> + <span><code class="code">-misel</code><a class="copiable-link" href="#index-misel"> ¶</a></span> +</dt> <dt><code class="code">-mno-isel</code></dt> <dd> +<p>This switch enables or disables the generation of ISEL instructions. </p> </dd> <dt> + <span><code class="code">-mvsx</code><a class="copiable-link" href="#index-mvsx"> ¶</a></span> +</dt> <dt><code class="code">-mno-vsx</code></dt> <dd> +<p>Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. </p> </dd> <dt> + <span><code class="code">-mcrypto</code><a class="copiable-link" href="#index-mcrypto"> ¶</a></span> +</dt> <dt><code class="code">-mno-crypto</code></dt> <dd> +<p>Enable the use (disable) of the built-in functions that allow direct access to the cryptographic instructions that were added in version 2.07 of the PowerPC ISA. </p> </dd> <dt> + <span><code class="code">-mhtm</code><a class="copiable-link" href="#index-mhtm"> ¶</a></span> +</dt> <dt><code class="code">-mno-htm</code></dt> <dd> +<p>Enable (disable) the use of the built-in functions that allow direct access to the Hardware Transactional Memory (HTM) instructions that were added in version 2.07 of the PowerPC ISA. </p> </dd> <dt> + <span><code class="code">-mpower8-fusion</code><a class="copiable-link" href="#index-mpower8-fusion"> ¶</a></span> +</dt> <dt><code class="code">-mno-power8-fusion</code></dt> <dd> +<p>Generate code that keeps (does not keeps) some integer operations adjacent so that the instructions can be fused together on power8 and later processors. </p> </dd> <dt> + <span><code class="code">-mpower8-vector</code><a class="copiable-link" href="#index-mpower8-vector"> ¶</a></span> +</dt> <dt><code class="code">-mno-power8-vector</code></dt> <dd> +<p>Generate code that uses (does not use) the vector and scalar instructions that were added in version 2.07 of the PowerPC ISA. Also enable the use of built-in functions that allow more direct access to the vector instructions. </p> </dd> <dt> + <span><code class="code">-mquad-memory</code><a class="copiable-link" href="#index-mquad-memory"> ¶</a></span> +</dt> <dt><code class="code">-mno-quad-memory</code></dt> <dd> +<p>Generate code that uses (does not use) the non-atomic quad word memory instructions. The <samp class="option">-mquad-memory</samp> option requires use of 64-bit mode. </p> </dd> <dt> + <span><code class="code">-mquad-memory-atomic</code><a class="copiable-link" href="#index-mquad-memory-atomic"> ¶</a></span> +</dt> <dt><code class="code">-mno-quad-memory-atomic</code></dt> <dd> +<p>Generate code that uses (does not use) the atomic quad word memory instructions. The <samp class="option">-mquad-memory-atomic</samp> option requires use of 64-bit mode. </p> </dd> <dt> + <span><code class="code">-mfloat128</code><a class="copiable-link" href="#index-mfloat128"> ¶</a></span> +</dt> <dt><code class="code">-mno-float128</code></dt> <dd> +<p>Enable/disable the <var class="var">__float128</var> keyword for IEEE 128-bit floating point and use either software emulation for IEEE 128-bit floating point or hardware instructions. </p> <p>The VSX instruction set (<samp class="option">-mvsx</samp>) must be enabled to use the IEEE 128-bit floating point support. The IEEE 128-bit floating point is only supported on Linux. </p> <p>The default for <samp class="option">-mfloat128</samp> is enabled on PowerPC Linux systems using the VSX instruction set, and disabled on other systems. </p> <p>If you use the ISA 3.0 instruction set (<samp class="option">-mpower9-vector</samp> or <samp class="option">-mcpu=power9</samp>) on a 64-bit system, the IEEE 128-bit floating point support will also enable the generation of ISA 3.0 IEEE 128-bit floating point instructions. Otherwise, if you do not specify to generate ISA 3.0 instructions or you are targeting a 32-bit big endian system, IEEE 128-bit floating point will be done with software emulation. </p> </dd> <dt> + <span><code class="code">-mfloat128-hardware</code><a class="copiable-link" href="#index-mfloat128-hardware"> ¶</a></span> +</dt> <dt><code class="code">-mno-float128-hardware</code></dt> <dd> +<p>Enable/disable using ISA 3.0 hardware instructions to support the <var class="var">__float128</var> data type. </p> <p>The default for <samp class="option">-mfloat128-hardware</samp> is enabled on PowerPC Linux systems using the ISA 3.0 instruction set, and disabled on other systems. </p> </dd> <dt> + <span><code class="code">-m32</code><a class="copiable-link" href="#index-m32"> ¶</a></span> +</dt> <dt><code class="code">-m64</code></dt> <dd> +<p>Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for <samp class="option">-mpowerpc64</samp>. </p> </dd> <dt> + <span><code class="code">-mfull-toc</code><a class="copiable-link" href="#index-mfull-toc"> ¶</a></span> +</dt> <dt><code class="code">-mno-fp-in-toc</code></dt> <dt><code class="code">-mno-sum-in-toc</code></dt> <dt><code class="code">-mminimal-toc</code></dt> <dd> +<p>Modify generation of the TOC (Table Of Contents), which is created for every executable file. The <samp class="option">-mfull-toc</samp> option is selected by default. In that case, GCC allocates at least one TOC entry for each unique non-automatic variable reference in your program. GCC also places floating-point constants in the TOC. However, only 16,384 entries are available in the TOC. </p> <p>If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the <samp class="option">-mno-fp-in-toc</samp> and <samp class="option">-mno-sum-in-toc</samp> options. <samp class="option">-mno-fp-in-toc</samp> prevents GCC from putting floating-point constants in the TOC and <samp class="option">-mno-sum-in-toc</samp> forces GCC to generate code to calculate the sum of an address and a constant at run time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space. </p> <p>If you still run out of space in the TOC even when you specify both of these options, specify <samp class="option">-mminimal-toc</samp> instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC produces code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently-executed code. </p> </dd> <dt> + <span><code class="code">-maix64</code><a class="copiable-link" href="#index-maix64"> ¶</a></span> +</dt> <dt><code class="code">-maix32</code></dt> <dd> +<p>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit <code class="code">long</code> type, and the infrastructure needed to support them. Specifying <samp class="option">-maix64</samp> implies <samp class="option">-mpowerpc64</samp>, while <samp class="option">-maix32</samp> disables the 64-bit ABI and implies <samp class="option">-mno-powerpc64</samp>. GCC defaults to <samp class="option">-maix32</samp>. </p> </dd> <dt> + <span><code class="code">-mxl-compat</code><a class="copiable-link" href="#index-mxl-compat"> ¶</a></span> +</dt> <dt><code class="code">-mno-xl-compat</code></dt> <dd> +<p>Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double. Use XL symbol names for long double support routines. </p> <p>The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating-point arguments that do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization. </p> </dd> <dt> +<span><code class="code">-mpe</code><a class="copiable-link" href="#index-mpe"> ¶</a></span> +</dt> <dd> +<p>Support <em class="dfn">IBM RS/6000 SP</em> <em class="dfn">Parallel Environment</em> (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location (<samp class="file">/usr/lpp/ppe.poe/</samp>), or the <samp class="file">specs</samp> file must be overridden with the <samp class="option">-specs=</samp> option to specify the appropriate directory location. The Parallel Environment does not support threads, so the <samp class="option">-mpe</samp> option and the <samp class="option">-pthread</samp> option are incompatible. </p> </dd> <dt> + <span><code class="code">-malign-natural</code><a class="copiable-link" href="#index-malign-natural"> ¶</a></span> +</dt> <dt><code class="code">-malign-power</code></dt> <dd> +<p>On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option <samp class="option">-malign-natural</samp> overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option <samp class="option">-malign-power</samp> instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI. </p> <p>On 64-bit Darwin, natural alignment is the default, and <samp class="option">-malign-power</samp> is not supported. </p> </dd> <dt> + <span><code class="code">-msoft-float</code><a class="copiable-link" href="#index-msoft-float-11"> ¶</a></span> +</dt> <dt><code class="code">-mhard-float</code></dt> <dd> +<p>Generate code that does not use (uses) the floating-point register set. Software floating-point emulation is provided if you use the <samp class="option">-msoft-float</samp> option, and pass the option to GCC when linking. </p> </dd> <dt> + <span><code class="code">-mmultiple</code><a class="copiable-link" href="#index-mmultiple"> ¶</a></span> +</dt> <dt><code class="code">-mno-multiple</code></dt> <dd> +<p>Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use <samp class="option">-mmultiple</samp> on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode. </p> </dd> <dt> + <span><code class="code">-mupdate</code><a class="copiable-link" href="#index-mupdate"> ¶</a></span> +</dt> <dt><code class="code">-mno-update</code></dt> <dd> +<p>Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use <samp class="option">-mno-update</samp>, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data. </p> </dd> <dt> + <span><code class="code">-mavoid-indexed-addresses</code><a class="copiable-link" href="#index-mavoid-indexed-addresses"> ¶</a></span> +</dt> <dt><code class="code">-mno-avoid-indexed-addresses</code></dt> <dd> +<p>Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 and disabled otherwise. </p> </dd> <dt> + <span><code class="code">-mfused-madd</code><a class="copiable-link" href="#index-mfused-madd-2"> ¶</a></span> +</dt> <dt><code class="code">-mno-fused-madd</code></dt> <dd> +<p>Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent <samp class="option">-mfused-madd</samp> option is now mapped to the machine-independent <samp class="option">-ffp-contract=fast</samp> option, and <samp class="option">-mno-fused-madd</samp> is mapped to <samp class="option">-ffp-contract=off</samp>. </p> </dd> <dt> + <span><code class="code">-mmulhw</code><a class="copiable-link" href="#index-mmulhw"> ¶</a></span> +</dt> <dt><code class="code">-mno-mulhw</code></dt> <dd> +<p>Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors. </p> </dd> <dt> + <span><code class="code">-mdlmzb</code><a class="copiable-link" href="#index-mdlmzb"> ¶</a></span> +</dt> <dt><code class="code">-mno-dlmzb</code></dt> <dd> +<p>Generate code that uses (does not use) the string-search ‘<samp class="samp">dlmzb</samp>’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors. </p> </dd> <dt> + <span><code class="code">-mno-bit-align</code><a class="copiable-link" href="#index-mno-bit-align"> ¶</a></span> +</dt> <dt><code class="code">-mbit-align</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field. </p> <p>For example, by default a structure containing nothing but 8 <code class="code">unsigned</code> bit-fields of length 1 is aligned to a 4-byte boundary and has a size of 4 bytes. By using <samp class="option">-mno-bit-align</samp>, the structure is aligned to a 1-byte boundary and is 1 byte in size. </p> </dd> <dt> + <span><code class="code">-mno-strict-align</code><a class="copiable-link" href="#index-mno-strict-align-2"> ¶</a></span> +</dt> <dt><code class="code">-mstrict-align</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references are handled by the system. </p> </dd> <dt> + <span><code class="code">-mrelocatable</code><a class="copiable-link" href="#index-mrelocatable"> ¶</a></span> +</dt> <dt><code class="code">-mno-relocatable</code></dt> <dd> +<p>Generate code that allows (does not allow) a static executable to be relocated to a different address at run time. A simple embedded PowerPC system loader should relocate the entire contents of <code class="code">.got2</code> and 4-byte locations listed in the <code class="code">.fixup</code> section, a table of 32-bit addresses generated by this option. For this to work, all objects linked together must be compiled with <samp class="option">-mrelocatable</samp> or <samp class="option">-mrelocatable-lib</samp>. <samp class="option">-mrelocatable</samp> code aligns the stack to an 8-byte boundary. </p> </dd> <dt> + <span><code class="code">-mrelocatable-lib</code><a class="copiable-link" href="#index-mrelocatable-lib"> ¶</a></span> +</dt> <dt><code class="code">-mno-relocatable-lib</code></dt> <dd> +<p>Like <samp class="option">-mrelocatable</samp>, <samp class="option">-mrelocatable-lib</samp> generates a <code class="code">.fixup</code> section to allow static executables to be relocated at run time, but <samp class="option">-mrelocatable-lib</samp> does not use the smaller stack alignment of <samp class="option">-mrelocatable</samp>. Objects compiled with <samp class="option">-mrelocatable-lib</samp> may be linked with objects compiled with any combination of the <samp class="option">-mrelocatable</samp> options. </p> </dd> <dt> + <span><code class="code">-mno-toc</code><a class="copiable-link" href="#index-mno-toc"> ¶</a></span> +</dt> <dt><code class="code">-mtoc</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program. </p> </dd> <dt> + <span><code class="code">-mlittle</code><a class="copiable-link" href="#index-mlittle"> ¶</a></span> +</dt> <dt><code class="code">-mlittle-endian</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the processor in little-endian mode. The <samp class="option">-mlittle-endian</samp> option is the same as <samp class="option">-mlittle</samp>. </p> </dd> <dt> + <span><code class="code">-mbig</code><a class="copiable-link" href="#index-mbig"> ¶</a></span> +</dt> <dt><code class="code">-mbig-endian</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the processor in big-endian mode. The <samp class="option">-mbig-endian</samp> option is the same as <samp class="option">-mbig</samp>. </p> </dd> <dt> +<span><code class="code">-mdynamic-no-pic</code><a class="copiable-link" href="#index-mdynamic-no-pic"> ¶</a></span> +</dt> <dd> +<p>On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries. </p> </dd> <dt> +<span><code class="code">-msingle-pic-base</code><a class="copiable-link" href="#index-msingle-pic-base-1"> ¶</a></span> +</dt> <dd> +<p>Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins. </p> </dd> <dt> +<span><code class="code">-mprioritize-restricted-insns=<var class="var">priority</var></code><a class="copiable-link" href="#index-mprioritize-restricted-insns"> ¶</a></span> +</dt> <dd> +<p>This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument <var class="var">priority</var> takes the value ‘<samp class="samp">0</samp>’, ‘<samp class="samp">1</samp>’, or ‘<samp class="samp">2</samp>’ to assign no, highest, or second-highest (respectively) priority to dispatch-slot restricted instructions. </p> </dd> <dt> +<span><code class="code">-msched-costly-dep=<var class="var">dependence_type</var></code><a class="copiable-link" href="#index-msched-costly-dep"> ¶</a></span> +</dt> <dd> +<p>This option controls which dependences are considered costly by the target during instruction scheduling. The argument <var class="var">dependence_type</var> takes one of the following values: </p> <dl class="table"> <dt>‘<samp class="samp">no</samp>’</dt> <dd> +<p>No dependence is costly. </p> </dd> <dt>‘<samp class="samp">all</samp>’</dt> <dd> +<p>All dependences are costly. </p> </dd> <dt>‘<samp class="samp">true_store_to_load</samp>’</dt> <dd> +<p>A true dependence from store to load is costly. </p> </dd> <dt>‘<samp class="samp">store_to_load</samp>’</dt> <dd> +<p>Any dependence from store to load is costly. </p> </dd> <dt><var class="var">number</var></dt> <dd><p>Any dependence for which the latency is greater than or equal to <var class="var">number</var> is costly. </p></dd> </dl> </dd> <dt> +<span><code class="code">-minsert-sched-nops=<var class="var">scheme</var></code><a class="copiable-link" href="#index-minsert-sched-nops"> ¶</a></span> +</dt> <dd> +<p>This option controls which NOP insertion scheme is used during the second scheduling pass. The argument <var class="var">scheme</var> takes one of the following values: </p> <dl class="table"> <dt>‘<samp class="samp">no</samp>’</dt> <dd> +<p>Don’t insert NOPs. </p> </dd> <dt>‘<samp class="samp">pad</samp>’</dt> <dd> +<p>Pad with NOPs any dispatch group that has vacant issue slots, according to the scheduler’s grouping. </p> </dd> <dt>‘<samp class="samp">regroup_exact</samp>’</dt> <dd> +<p>Insert NOPs to force costly dependent insns into separate groups. Insert exactly as many NOPs as needed to force an insn to a new group, according to the estimated processor grouping. </p> </dd> <dt><var class="var">number</var></dt> <dd><p>Insert NOPs to force costly dependent insns into separate groups. Insert <var class="var">number</var> NOPs to force an insn to a new group. </p></dd> </dl> </dd> <dt> +<span><code class="code">-mcall-sysv</code><a class="copiable-link" href="#index-mcall-sysv"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code using calling conventions that adhere to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using ‘<samp class="samp">powerpc-*-eabiaix</samp>’. </p> </dd> <dt> + <span><code class="code">-mcall-sysv-eabi</code><a class="copiable-link" href="#index-mcall-sysv-eabi"> ¶</a></span> +</dt> <dt><code class="code">-mcall-eabi</code></dt> <dd> +<p>Specify both <samp class="option">-mcall-sysv</samp> and <samp class="option">-meabi</samp> options. </p> </dd> <dt> +<span><code class="code">-mcall-sysv-noeabi</code><a class="copiable-link" href="#index-mcall-sysv-noeabi"> ¶</a></span> +</dt> <dd> +<p>Specify both <samp class="option">-mcall-sysv</samp> and <samp class="option">-mno-eabi</samp> options. </p> </dd> <dt> +<span><code class="code">-mcall-aixdesc</code><a class="copiable-link" href="#index-mcall-aixdesc"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the AIX operating system. </p> </dd> <dt> +<span><code class="code">-mcall-linux</code><a class="copiable-link" href="#index-mcall-linux"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system. </p> </dd> <dt> +<span><code class="code">-mcall-freebsd</code><a class="copiable-link" href="#index-mcall-freebsd"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the FreeBSD operating system. </p> </dd> <dt> +<span><code class="code">-mcall-netbsd</code><a class="copiable-link" href="#index-mcall-netbsd"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system. </p> </dd> <dt> +<span><code class="code">-mcall-openbsd</code><a class="copiable-link" href="#index-mcall-openbsd"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system. </p> </dd> <dt> +<span><code class="code">-mtraceback=<var class="var">traceback_type</var></code><a class="copiable-link" href="#index-mtraceback"> ¶</a></span> +</dt> <dd> +<p>Select the type of traceback table. Valid values for <var class="var">traceback_type</var> are ‘<samp class="samp">full</samp>’, ‘<samp class="samp">part</samp>’, and ‘<samp class="samp">no</samp>’. </p> </dd> <dt> +<span><code class="code">-maix-struct-return</code><a class="copiable-link" href="#index-maix-struct-return"> ¶</a></span> +</dt> <dd> +<p>Return all structures in memory (as specified by the AIX ABI). </p> </dd> <dt> +<span><code class="code">-msvr4-struct-return</code><a class="copiable-link" href="#index-msvr4-struct-return"> ¶</a></span> +</dt> <dd> +<p>Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI). </p> </dd> <dt> +<span><code class="code">-mabi=<var class="var">abi-type</var></code><a class="copiable-link" href="#index-mabi-5"> ¶</a></span> +</dt> <dd> +<p>Extend the current ABI with a particular extension, or remove such extension. Valid values are: ‘<samp class="samp">altivec</samp>’, ‘<samp class="samp">no-altivec</samp>’, ‘<samp class="samp">ibmlongdouble</samp>’, ‘<samp class="samp">ieeelongdouble</samp>’, ‘<samp class="samp">elfv1</samp>’, ‘<samp class="samp">elfv2</samp>’, and for AIX: ‘<samp class="samp">vec-extabi</samp>’, ‘<samp class="samp">vec-default</samp>’. </p> </dd> <dt> +<span><code class="code">-mabi=ibmlongdouble</code><a class="copiable-link" href="#index-mabi_003dibmlongdouble"> ¶</a></span> +</dt> <dd> +<p>Change the current ABI to use IBM extended-precision long double. This is not likely to work if your system defaults to using IEEE extended-precision long double. If you change the long double type from IEEE extended-precision, the compiler will issue a warning unless you use the <samp class="option">-Wno-psabi</samp> option. Requires <samp class="option">-mlong-double-128</samp> to be enabled. </p> </dd> <dt> +<span><code class="code">-mabi=ieeelongdouble</code><a class="copiable-link" href="#index-mabi_003dieeelongdouble"> ¶</a></span> +</dt> <dd> +<p>Change the current ABI to use IEEE extended-precision long double. This is not likely to work if your system defaults to using IBM extended-precision long double. If you change the long double type from IBM extended-precision, the compiler will issue a warning unless you use the <samp class="option">-Wno-psabi</samp> option. Requires <samp class="option">-mlong-double-128</samp> to be enabled. </p> </dd> <dt> +<span><code class="code">-mabi=elfv1</code><a class="copiable-link" href="#index-mabi_003delfv1"> ¶</a></span> +</dt> <dd> +<p>Change the current ABI to use the ELFv1 ABI. This is the default ABI for big-endian PowerPC 64-bit Linux. Overriding the default ABI requires special system support and is likely to fail in spectacular ways. </p> </dd> <dt> +<span><code class="code">-mabi=elfv2</code><a class="copiable-link" href="#index-mabi_003delfv2"> ¶</a></span> +</dt> <dd> +<p>Change the current ABI to use the ELFv2 ABI. This is the default ABI for little-endian PowerPC 64-bit Linux. Overriding the default ABI requires special system support and is likely to fail in spectacular ways. </p> </dd> <dt> + <span><code class="code">-mgnu-attribute</code><a class="copiable-link" href="#index-mgnu-attribute"> ¶</a></span> +</dt> <dt><code class="code">-mno-gnu-attribute</code></dt> <dd> +<p>Emit .gnu_attribute assembly directives to set tag/value pairs in a .gnu.attributes section that specify ABI variations in function parameters or return values. </p> </dd> <dt> + <span><code class="code">-mprototype</code><a class="copiable-link" href="#index-mprototype"> ¶</a></span> +</dt> <dt><code class="code">-mno-prototype</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped. Otherwise, the compiler must insert an instruction before every non-prototyped call to set or clear bit 6 of the condition code register (<code class="code">CR</code>) to indicate whether floating-point values are passed in the floating-point registers in case the function takes variable arguments. With <samp class="option">-mprototype</samp>, only calls to prototyped variable argument functions set or clear the bit. </p> </dd> <dt> +<span><code class="code">-msim</code><a class="copiable-link" href="#index-msim-7"> ¶</a></span> +</dt> <dd> +<p>On embedded PowerPC systems, assume that the startup module is called <samp class="file">sim-crt0.o</samp> and that the standard C libraries are <samp class="file">libsim.a</samp> and <samp class="file">libc.a</samp>. This is the default for ‘<samp class="samp">powerpc-*-eabisim</samp>’ configurations. </p> </dd> <dt> +<span><code class="code">-mmvme</code><a class="copiable-link" href="#index-mmvme"> ¶</a></span> +</dt> <dd> +<p>On embedded PowerPC systems, assume that the startup module is called <samp class="file">crt0.o</samp> and the standard C libraries are <samp class="file">libmvme.a</samp> and <samp class="file">libc.a</samp>. </p> </dd> <dt> +<span><code class="code">-mads</code><a class="copiable-link" href="#index-mads"> ¶</a></span> +</dt> <dd> +<p>On embedded PowerPC systems, assume that the startup module is called <samp class="file">crt0.o</samp> and the standard C libraries are <samp class="file">libads.a</samp> and <samp class="file">libc.a</samp>. </p> </dd> <dt> +<span><code class="code">-myellowknife</code><a class="copiable-link" href="#index-myellowknife"> ¶</a></span> +</dt> <dd> +<p>On embedded PowerPC systems, assume that the startup module is called <samp class="file">crt0.o</samp> and the standard C libraries are <samp class="file">libyk.a</samp> and <samp class="file">libc.a</samp>. </p> </dd> <dt> +<span><code class="code">-mvxworks</code><a class="copiable-link" href="#index-mvxworks"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system. </p> </dd> <dt> +<span><code class="code">-memb</code><a class="copiable-link" href="#index-memb"> ¶</a></span> +</dt> <dd> +<p>On embedded PowerPC systems, set the <code class="code">PPC_EMB</code> bit in the ELF flags header to indicate that ‘<samp class="samp">eabi</samp>’ extended relocations are used. </p> </dd> <dt> + <span><code class="code">-meabi</code><a class="copiable-link" href="#index-meabi"> ¶</a></span> +</dt> <dt><code class="code">-mno-eabi</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (EABI), which is a set of modifications to the System V.4 specifications. Selecting <samp class="option">-meabi</samp> means that the stack is aligned to an 8-byte boundary, a function <code class="code">__eabi</code> is called from <code class="code">main</code> to set up the EABI environment, and the <samp class="option">-msdata</samp> option can use both <code class="code">r2</code> and <code class="code">r13</code> to point to two separate small data areas. Selecting <samp class="option">-mno-eabi</samp> means that the stack is aligned to a 16-byte boundary, no EABI initialization function is called from <code class="code">main</code>, and the <samp class="option">-msdata</samp> option only uses <code class="code">r13</code> to point to a single small data area. The <samp class="option">-meabi</samp> option is on by default if you configured GCC using one of the ‘<samp class="samp">powerpc*-*-eabi*</samp>’ options. </p> </dd> <dt> +<span><code class="code">-msdata=eabi</code><a class="copiable-link" href="#index-msdata_003deabi"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems, put small initialized <code class="code">const</code> global and static data in the <code class="code">.sdata2</code> section, which is pointed to by register <code class="code">r2</code>. Put small initialized non-<code class="code">const</code> global and static data in the <code class="code">.sdata</code> section, which is pointed to by register <code class="code">r13</code>. Put small uninitialized global and static data in the <code class="code">.sbss</code> section, which is adjacent to the <code class="code">.sdata</code> section. The <samp class="option">-msdata=eabi</samp> option is incompatible with the <samp class="option">-mrelocatable</samp> option. The <samp class="option">-msdata=eabi</samp> option also sets the <samp class="option">-memb</samp> option. </p> </dd> <dt> +<span><code class="code">-msdata=sysv</code><a class="copiable-link" href="#index-msdata_003dsysv"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems, put small global and static data in the <code class="code">.sdata</code> section, which is pointed to by register <code class="code">r13</code>. Put small uninitialized global and static data in the <code class="code">.sbss</code> section, which is adjacent to the <code class="code">.sdata</code> section. The <samp class="option">-msdata=sysv</samp> option is incompatible with the <samp class="option">-mrelocatable</samp> option. </p> </dd> <dt> + <span><code class="code">-msdata=default</code><a class="copiable-link" href="#index-msdata_003ddefault-1"> ¶</a></span> +</dt> <dt><code class="code">-msdata</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems, if <samp class="option">-meabi</samp> is used, compile code the same as <samp class="option">-msdata=eabi</samp>, otherwise compile code the same as <samp class="option">-msdata=sysv</samp>. </p> </dd> <dt> +<span><code class="code">-msdata=data</code><a class="copiable-link" href="#index-msdata_003ddata"> ¶</a></span> +</dt> <dd> +<p>On System V.4 and embedded PowerPC systems, put small global data in the <code class="code">.sdata</code> section. Put small uninitialized global data in the <code class="code">.sbss</code> section. Do not use register <code class="code">r13</code> to address small data however. This is the default behavior unless other <samp class="option">-msdata</samp> options are used. </p> </dd> <dt> + <span><code class="code">-msdata=none</code><a class="copiable-link" href="#index-msdata_003dnone-2"> ¶</a></span> +</dt> <dt><code class="code">-mno-sdata</code></dt> <dd> +<p>On embedded PowerPC systems, put all initialized global and static data in the <code class="code">.data</code> section, and all uninitialized data in the <code class="code">.bss</code> section. </p> </dd> <dt> + <span><code class="code">-mreadonly-in-sdata</code><a class="copiable-link" href="#index-mreadonly-in-sdata"> ¶</a></span> +</dt> <dd> +<p>Put read-only objects in the <code class="code">.sdata</code> section as well. This is the default. </p> </dd> <dt> +<span><code class="code">-mblock-move-inline-limit=<var class="var">num</var></code><a class="copiable-link" href="#index-mblock-move-inline-limit"> ¶</a></span> +</dt> <dd> +<p>Inline all block moves (such as calls to <code class="code">memcpy</code> or structure copies) less than or equal to <var class="var">num</var> bytes. The minimum value for <var class="var">num</var> is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets. The default value is target-specific. </p> </dd> <dt> +<span><code class="code">-mblock-compare-inline-limit=<var class="var">num</var></code><a class="copiable-link" href="#index-mblock-compare-inline-limit"> ¶</a></span> +</dt> <dd> +<p>Generate non-looping inline code for all block compares (such as calls to <code class="code">memcmp</code> or structure compares) less than or equal to <var class="var">num</var> bytes. If <var class="var">num</var> is 0, all inline expansion (non-loop and loop) of block compare is disabled. The default value is target-specific. </p> </dd> <dt> +<span><code class="code">-mblock-compare-inline-loop-limit=<var class="var">num</var></code><a class="copiable-link" href="#index-mblock-compare-inline-loop-limit"> ¶</a></span> +</dt> <dd> +<p>Generate an inline expansion using loop code for all block compares that are less than or equal to <var class="var">num</var> bytes, but greater than the limit for non-loop inline block compare expansion. If the block length is not constant, at most <var class="var">num</var> bytes will be compared before <code class="code">memcmp</code> is called to compare the remainder of the block. The default value is target-specific. </p> </dd> <dt> +<span><code class="code">-mstring-compare-inline-limit=<var class="var">num</var></code><a class="copiable-link" href="#index-mstring-compare-inline-limit"> ¶</a></span> +</dt> <dd> +<p>Compare at most <var class="var">num</var> string bytes with inline code. If the difference or end of string is not found at the end of the inline compare a call to <code class="code">strcmp</code> or <code class="code">strncmp</code> will take care of the rest of the comparison. The default is 64 bytes. </p> </dd> <dt> + <span><code class="code">-G <var class="var">num</var></code><a class="copiable-link" href="#index-G-4"> ¶</a></span> +</dt> <dd> +<p>On embedded PowerPC systems, put global and static items less than or equal to <var class="var">num</var> bytes into the small data or BSS sections instead of the normal data or BSS section. By default, <var class="var">num</var> is 8. The <samp class="option">-G <var class="var">num</var></samp> switch is also passed to the linker. All modules should be compiled with the same <samp class="option">-G <var class="var">num</var></samp> value. </p> </dd> <dt> + <span><code class="code">-mregnames</code><a class="copiable-link" href="#index-mregnames"> ¶</a></span> +</dt> <dt><code class="code">-mno-regnames</code></dt> <dd> +<p>On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms. </p> </dd> <dt> + <span><code class="code">-mlongcall</code><a class="copiable-link" href="#index-mlongcall"> ¶</a></span> +</dt> <dt><code class="code">-mno-longcall</code></dt> <dd> +<p>By default assume that all calls are far away so that a longer and more expensive calling sequence is required. This is required for calls farther than 32 megabytes (33,554,432 bytes) from the current location. A short call is generated if the compiler knows the call cannot be that far away. This setting can be overridden by the <code class="code">shortcall</code> function attribute, or by <code class="code">#pragma +longcall(0)</code>. </p> <p>Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well. </p> <p>On PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU linkers, GCC can generate long calls using an inline PLT call sequence (see <samp class="option">-mpltseq</samp>). PowerPC with <samp class="option">-mbss-plt</samp> and PowerPC64 ELFv1 (big-endian) do not support inline PLT calls. </p> <p>On Darwin/PPC systems, <code class="code">#pragma longcall</code> generates <code class="code">jbsr +callee, L42</code>, plus a <em class="dfn">branch island</em> (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a <code class="code">bl +callee</code> if the PPC <code class="code">bl</code> instruction reaches the callee directly; otherwise, the linker generates <code class="code">bl L42</code> to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it. </p> <p>On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it. </p> <p>In the future, GCC may ignore all longcall specifications when the linker is known to generate glue. </p> </dd> <dt> + <span><code class="code">-mpltseq</code><a class="copiable-link" href="#index-mpltseq"> ¶</a></span> +</dt> <dt><code class="code">-mno-pltseq</code></dt> <dd> +<p>Implement (do not implement) -fno-plt and long calls using an inline PLT call sequence that supports lazy linking and long calls to functions in dlopen’d shared libraries. Inline PLT calls are only supported on PowerPC64 ELFv2 and 32-bit PowerPC systems with newer GNU linkers, and are enabled by default if the support is detected when configuring GCC, and, in the case of 32-bit PowerPC, if GCC is configured with <samp class="option">--enable-secureplt</samp>. <samp class="option">-mpltseq</samp> code and <samp class="option">-mbss-plt</samp> 32-bit PowerPC relocatable objects may not be linked together. </p> </dd> <dt> + <span><code class="code">-mtls-markers</code><a class="copiable-link" href="#index-mtls-markers"> ¶</a></span> +</dt> <dt><code class="code">-mno-tls-markers</code></dt> <dd> +<p>Mark (do not mark) calls to <code class="code">__tls_get_addr</code> with a relocation specifying the function argument. The relocation allows the linker to reliably associate function call with argument setup instructions for TLS optimization, which in turn allows GCC to better schedule the sequence. </p> </dd> <dt> +<span><code class="code">-mrecip</code><a class="copiable-link" href="#index-mrecip"> ¶</a></span> +</dt> <dt><code class="code">-mno-recip</code></dt> <dd> +<p>This option enables use of the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments. You should use the <samp class="option">-ffast-math</samp> option when using <samp class="option">-mrecip</samp> (or at least <samp class="option">-funsafe-math-optimizations</samp>, <samp class="option">-ffinite-math-only</samp>, <samp class="option">-freciprocal-math</samp> and <samp class="option">-fno-trapping-math</samp>). Note that while the throughput of the sequence is generally higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots. </p> </dd> <dt> +<span><code class="code">-mrecip=<var class="var">opt</var></code><a class="copiable-link" href="#index-mrecip_003dopt"> ¶</a></span> +</dt> <dd> +<p>This option controls which reciprocal estimate instructions may be used. <var class="var">opt</var> is a comma-separated list of options, which may be preceded by a <code class="code">!</code> to invert the option: </p> <dl class="table"> <dt>‘<samp class="samp">all</samp>’</dt> <dd> +<p>Enable all estimate instructions. </p> </dd> <dt>‘<samp class="samp">default</samp>’</dt> <dd> +<p>Enable the default instructions, equivalent to <samp class="option">-mrecip</samp>. </p> </dd> <dt>‘<samp class="samp">none</samp>’</dt> <dd> +<p>Disable all estimate instructions, equivalent to <samp class="option">-mno-recip</samp>. </p> </dd> <dt>‘<samp class="samp">div</samp>’</dt> <dd> +<p>Enable the reciprocal approximation instructions for both single and double precision. </p> </dd> <dt>‘<samp class="samp">divf</samp>’</dt> <dd> +<p>Enable the single-precision reciprocal approximation instructions. </p> </dd> <dt>‘<samp class="samp">divd</samp>’</dt> <dd> +<p>Enable the double-precision reciprocal approximation instructions. </p> </dd> <dt>‘<samp class="samp">rsqrt</samp>’</dt> <dd> +<p>Enable the reciprocal square root approximation instructions for both single and double precision. </p> </dd> <dt>‘<samp class="samp">rsqrtf</samp>’</dt> <dd> +<p>Enable the single-precision reciprocal square root approximation instructions. </p> </dd> <dt>‘<samp class="samp">rsqrtd</samp>’</dt> <dd> +<p>Enable the double-precision reciprocal square root approximation instructions. </p> </dd> </dl> <p>So, for example, <samp class="option">-mrecip=all,!rsqrtd</samp> enables all of the reciprocal estimate instructions, except for the <code class="code">FRSQRTE</code>, <code class="code">XSRSQRTEDP</code>, and <code class="code">XVRSQRTEDP</code> instructions which handle the double-precision reciprocal square root calculations. </p> </dd> <dt> +<span><code class="code">-mrecip-precision</code><a class="copiable-link" href="#index-mrecip-precision"> ¶</a></span> +</dt> <dt><code class="code">-mno-recip-precision</code></dt> <dd> +<p>Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI. Selecting <samp class="option">-mcpu=power6</samp>, <samp class="option">-mcpu=power7</samp> or <samp class="option">-mcpu=power8</samp> automatically selects <samp class="option">-mrecip-precision</samp>. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps. </p> </dd> <dt> +<span><code class="code">-mveclibabi=<var class="var">type</var></code><a class="copiable-link" href="#index-mveclibabi"> ¶</a></span> +</dt> <dd> +<p>Specifies the ABI type to use for vectorizing intrinsics using an external library. The only type supported at present is ‘<samp class="samp">mass</samp>’, which specifies to use IBM’s Mathematical Acceleration Subsystem (MASS) libraries for vectorizing intrinsics using external libraries. GCC currently emits calls to <code class="code">acosd2</code>, <code class="code">acosf4</code>, <code class="code">acoshd2</code>, <code class="code">acoshf4</code>, <code class="code">asind2</code>, <code class="code">asinf4</code>, <code class="code">asinhd2</code>, <code class="code">asinhf4</code>, <code class="code">atan2d2</code>, <code class="code">atan2f4</code>, <code class="code">atand2</code>, <code class="code">atanf4</code>, <code class="code">atanhd2</code>, <code class="code">atanhf4</code>, <code class="code">cbrtd2</code>, <code class="code">cbrtf4</code>, <code class="code">cosd2</code>, <code class="code">cosf4</code>, <code class="code">coshd2</code>, <code class="code">coshf4</code>, <code class="code">erfcd2</code>, <code class="code">erfcf4</code>, <code class="code">erfd2</code>, <code class="code">erff4</code>, <code class="code">exp2d2</code>, <code class="code">exp2f4</code>, <code class="code">expd2</code>, <code class="code">expf4</code>, <code class="code">expm1d2</code>, <code class="code">expm1f4</code>, <code class="code">hypotd2</code>, <code class="code">hypotf4</code>, <code class="code">lgammad2</code>, <code class="code">lgammaf4</code>, <code class="code">log10d2</code>, <code class="code">log10f4</code>, <code class="code">log1pd2</code>, <code class="code">log1pf4</code>, <code class="code">log2d2</code>, <code class="code">log2f4</code>, <code class="code">logd2</code>, <code class="code">logf4</code>, <code class="code">powd2</code>, <code class="code">powf4</code>, <code class="code">sind2</code>, <code class="code">sinf4</code>, <code class="code">sinhd2</code>, <code class="code">sinhf4</code>, <code class="code">sqrtd2</code>, <code class="code">sqrtf4</code>, <code class="code">tand2</code>, <code class="code">tanf4</code>, <code class="code">tanhd2</code>, and <code class="code">tanhf4</code> when generating code for power7. Both <samp class="option">-ftree-vectorize</samp> and <samp class="option">-funsafe-math-optimizations</samp> must also be enabled. The MASS libraries must be specified at link time. </p> </dd> <dt> +<span><code class="code">-mfriz</code><a class="copiable-link" href="#index-mfriz"> ¶</a></span> +</dt> <dt><code class="code">-mno-friz</code></dt> <dd> +<p>Generate (do not generate) the <code class="code">friz</code> instruction when the <samp class="option">-funsafe-math-optimizations</samp> option is used to optimize rounding of floating-point values to 64-bit integer and back to floating point. The <code class="code">friz</code> instruction does not return the same value if the floating-point number is too large to fit in an integer. </p> </dd> <dt> +<span><code class="code">-mpointers-to-nested-functions</code><a class="copiable-link" href="#index-mpointers-to-nested-functions"> ¶</a></span> +</dt> <dt><code class="code">-mno-pointers-to-nested-functions</code></dt> <dd> +<p>Generate (do not generate) code to load up the static chain register (<code class="code">r11</code>) when calling through a pointer on AIX and 64-bit Linux systems where a function pointer points to a 3-word descriptor giving the function address, TOC value to be loaded in register <code class="code">r2</code>, and static chain value to be loaded in register <code class="code">r11</code>. The <samp class="option">-mpointers-to-nested-functions</samp> is on by default. You cannot call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if you use <samp class="option">-mno-pointers-to-nested-functions</samp>. </p> </dd> <dt> +<span><code class="code">-msave-toc-indirect</code><a class="copiable-link" href="#index-msave-toc-indirect"> ¶</a></span> +</dt> <dt><code class="code">-mno-save-toc-indirect</code></dt> <dd> +<p>Generate (do not generate) code to save the TOC value in the reserved stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The <samp class="option">-mno-save-toc-indirect</samp> option is the default. </p> </dd> <dt> +<span><code class="code">-mcompat-align-parm</code><a class="copiable-link" href="#index-mcompat-align-parm"> ¶</a></span> +</dt> <dt><code class="code">-mno-compat-align-parm</code></dt> <dd> +<p>Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions of GCC. </p> <p>Older versions of GCC (prior to 4.9.0) incorrectly did not align a structure parameter on a 128-bit boundary when that structure contained a member requiring 128-bit alignment. This is corrected in more recent versions of GCC. This option may be used to generate code that is compatible with functions compiled with older versions of GCC. </p> <p>The <samp class="option">-mno-compat-align-parm</samp> option is the default. </p> </dd> <dt> + <span><code class="code">-mstack-protector-guard=<var class="var">guard</var></code><a class="copiable-link" href="#index-mstack-protector-guard-3"> ¶</a></span> +</dt> <dt><code class="code">-mstack-protector-guard-reg=<var class="var">reg</var></code></dt> <dt><code class="code">-mstack-protector-guard-offset=<var class="var">offset</var></code></dt> <dt><code class="code">-mstack-protector-guard-symbol=<var class="var">symbol</var></code></dt> <dd> +<p>Generate stack protection code using canary at <var class="var">guard</var>. Supported locations are ‘<samp class="samp">global</samp>’ for global canary or ‘<samp class="samp">tls</samp>’ for per-thread canary in the TLS block (the default with GNU libc version 2.4 or later). </p> <p>With the latter choice the options <samp class="option">-mstack-protector-guard-reg=<var class="var">reg</var></samp> and <samp class="option">-mstack-protector-guard-offset=<var class="var">offset</var></samp> furthermore specify which register to use as base register for reading the canary, and from what offset from that base register. The default for those is as specified in the relevant ABI. <samp class="option">-mstack-protector-guard-symbol=<var class="var">symbol</var></samp> overrides the offset with a symbol reference to a canary in the TLS block. </p> </dd> <dt> + <span><code class="code">-mpcrel</code><a class="copiable-link" href="#index-mpcrel-1"> ¶</a></span> +</dt> <dt><code class="code">-mno-pcrel</code></dt> <dd> +<p>Generate (do not generate) pc-relative addressing. The <samp class="option">-mpcrel</samp> option requires that the medium code model (<samp class="option">-mcmodel=medium</samp>) and prefixed addressing (<samp class="option">-mprefixed</samp>) options are enabled. </p> </dd> <dt> + <span><code class="code">-mprefixed</code><a class="copiable-link" href="#index-mprefixed"> ¶</a></span> +</dt> <dt><code class="code">-mno-prefixed</code></dt> <dd> +<p>Generate (do not generate) addressing modes using prefixed load and store instructions. The <samp class="option">-mprefixed</samp> option requires that the option <samp class="option">-mcpu=power10</samp> (or later) is enabled. </p> </dd> <dt> + <span><code class="code">-mmma</code><a class="copiable-link" href="#index-mmma"> ¶</a></span> +</dt> <dt><code class="code">-mno-mma</code></dt> <dd> +<p>Generate (do not generate) the MMA instructions. The <samp class="option">-mma</samp> option requires that the option <samp class="option">-mcpu=power10</samp> (or later) is enabled. </p> </dd> <dt> + <span><code class="code">-mrop-protect</code><a class="copiable-link" href="#index-mrop-protect"> ¶</a></span> +</dt> <dt><code class="code">-mno-rop-protect</code></dt> <dd> +<p>Generate (do not generate) ROP protection instructions when the target processor supports them. Currently this option disables the shrink-wrap optimization (<samp class="option">-fshrink-wrap</samp>). </p> </dd> <dt> + <span><code class="code">-mprivileged</code><a class="copiable-link" href="#index-mprivileged"> ¶</a></span> +</dt> <dt><code class="code">-mno-privileged</code></dt> <dd> +<p>Generate (do not generate) code that will run in privileged state. </p> </dd> <dt> + <span><code class="code">-mblock-ops-unaligned-vsx</code><a class="copiable-link" href="#index-block-ops-unaligned-vsx"> ¶</a></span> +</dt> <dt><code class="code">-mno-block-ops-unaligned-vsx</code></dt> <dd> +<p>Generate (do not generate) unaligned vsx loads and stores for inline expansion of <code class="code">memcpy</code> and <code class="code">memmove</code>. </p> </dd> <dt><code class="code">--param rs6000-vect-unroll-limit=</code></dt> <dd> +<p>The vectorizer will check with target information to determine whether it would be beneficial to unroll the main vectorized loop and by how much. This parameter sets the upper bound of how much the vectorizer will unroll the main loop. The default value is four. </p> </dd> </dl> </div> <div class="nav-panel"> <p> Next: <a href="rx-options">RX Options</a>, Previous: <a href="rl78-options">RL78 Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution"> + <p class="_attribution-p"> + © Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br> + <a href="https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/RS_002f6000-and-PowerPC-Options.html" class="_attribution-link">https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/RS_002f6000-and-PowerPC-Options.html</a> + </p> +</div> |