path: root/devdocs/gcc~13/aarch64-options.html

<div class="subsection-level-extent" id="AArch64-Options"> <div class="nav-panel"> <p> Next: <a href="adapteva-epiphany-options" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="AArch64-Options-1"><span>3.19.1 AArch64 Options<a class="copiable-link" href="#AArch64-Options-1"> ¶</a></span></h1>  <p>These options are defined for AArch64 implementations: </p> <dl class="table"> <dt>
<span><code class="code">-mabi=<var class="var">name</var></code><a class="copiable-link" href="#index-mabi"> ¶</a></span>
</dt> <dd>
<p>Generate code for the specified data model. Permissible values are ‘<samp class="samp">ilp32</samp>’ for SysV-like data model where int, long int and pointers are 32 bits, and ‘<samp class="samp">lp64</samp>’ for SysV-like data model where int is 32 bits, but long int and pointers are 64 bits. </p> <p>The default depends on the specific target configuration. Note that the LP64 and ILP32 ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries. </p> </dd> <dt>
<span><code class="code">-mbig-endian</code><a class="copiable-link" href="#index-mbig-endian"> ¶</a></span>
</dt> <dd>
<p>Generate big-endian code. This is the default when GCC is configured for an ‘<samp class="samp">aarch64_be-*-*</samp>’ target. </p> </dd> <dt>
<span><code class="code">-mgeneral-regs-only</code><a class="copiable-link" href="#index-mgeneral-regs-only"> ¶</a></span>
</dt> <dd>
<p>Generate code which uses only the general-purpose registers. This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler. </p> </dd> <dt>
<span><code class="code">-mlittle-endian</code><a class="copiable-link" href="#index-mlittle-endian"> ¶</a></span>
</dt> <dd>
<p>Generate little-endian code. This is the default when GCC is configured for an ‘<samp class="samp">aarch64-*-*</samp>’ but not an ‘<samp class="samp">aarch64_be-*-*</samp>’ target. </p> </dd> <dt>
<span><code class="code">-mcmodel=tiny</code><a class="copiable-link" href="#index-mcmodel_003dtiny"> ¶</a></span>
</dt> <dd>
<p>Generate code for the tiny code model. The program and its statically defined symbols must be within 1MB of each other. Programs can be statically or dynamically linked. </p> </dd> <dt>
<span><code class="code">-mcmodel=small</code><a class="copiable-link" href="#index-mcmodel_003dsmall"> ¶</a></span>
</dt> <dd>
<p>Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Programs can be statically or dynamically linked. This is the default code model. </p> </dd> <dt>
<span><code class="code">-mcmodel=large</code><a class="copiable-link" href="#index-mcmodel_003dlarge"> ¶</a></span>
</dt> <dd>
<p>Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Programs can be statically linked only. The <samp class="option">-mcmodel=large</samp> option is incompatible with <samp class="option">-mabi=ilp32</samp>, <samp class="option">-fpic</samp> and <samp class="option">-fPIC</samp>. </p> </dd> <dt>
 <span><code class="code">-mstrict-align</code><a class="copiable-link" href="#index-mstrict-align"> ¶</a></span>
</dt> <dt><code class="code">-mno-strict-align</code></dt> <dd>
<p>Avoid or allow generating memory accesses that may not be aligned on a natural object boundary as described in the architecture specification. </p> </dd> <dt>
 <span><code class="code">-momit-leaf-frame-pointer</code><a class="copiable-link" href="#index-momit-leaf-frame-pointer"> ¶</a></span>
</dt> <dt><code class="code">-mno-omit-leaf-frame-pointer</code></dt> <dd>
<p>Omit or keep the frame pointer in leaf functions. The former behavior is the default. </p> </dd> <dt>
  <span><code class="code">-mstack-protector-guard=<var class="var">guard</var></code><a class="copiable-link" href="#index-mstack-protector-guard"> ¶</a></span>
</dt> <dt><code class="code">-mstack-protector-guard-reg=<var class="var">reg</var></code></dt> <dt><code class="code">-mstack-protector-guard-offset=<var class="var">offset</var></code></dt> <dd>
<p>Generate stack protection code using canary at <var class="var">guard</var>. Supported locations are ‘<samp class="samp">global</samp>’ for a global canary or ‘<samp class="samp">sysreg</samp>’ for a canary in an appropriate system register. </p> <p>With the latter choice the options <samp class="option">-mstack-protector-guard-reg=<var class="var">reg</var></samp> and <samp class="option">-mstack-protector-guard-offset=<var class="var">offset</var></samp> furthermore specify which system register to use as base register for reading the canary, and from what offset from that base register. There is no default register or offset as this is entirely for use within the Linux kernel. </p> </dd> <dt>
<span><code class="code">-mtls-dialect=desc</code><a class="copiable-link" href="#index-mtls-dialect_003ddesc"> ¶</a></span>
</dt> <dd>
<p>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default. </p> </dd> <dt>
<span><code class="code">-mtls-dialect=traditional</code><a class="copiable-link" href="#index-mtls-dialect_003dtraditional"> ¶</a></span>
</dt> <dd>
<p>Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables. </p> </dd> <dt>
<span><code class="code">-mtls-size=<var class="var">size</var></code><a class="copiable-link" href="#index-mtls-size"> ¶</a></span>
</dt> <dd>
<p>Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. This option requires binutils 2.26 or newer. </p> </dd> <dt>
 <span><code class="code">-mfix-cortex-a53-835769</code><a class="copiable-link" href="#index-mfix-cortex-a53-835769"> ¶</a></span>
</dt> <dt><code class="code">-mno-fix-cortex-a53-835769</code></dt> <dd>
<p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This involves inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions. </p> </dd> <dt>
 <span><code class="code">-mfix-cortex-a53-843419</code><a class="copiable-link" href="#index-mfix-cortex-a53-843419"> ¶</a></span>
</dt> <dt><code class="code">-mno-fix-cortex-a53-843419</code></dt> <dd>
<p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. This erratum workaround is made at link time and this will only pass the corresponding flag to the linker. </p> </dd> <dt>
 <span><code class="code">-mlow-precision-recip-sqrt</code><a class="copiable-link" href="#index-mlow-precision-recip-sqrt"> ¶</a></span>
</dt> <dt><code class="code">-mno-low-precision-recip-sqrt</code></dt> <dd>
<p>Enable or disable the reciprocal square root approximation. This option only has an effect if <samp class="option">-ffast-math</samp> or <samp class="option">-funsafe-math-optimizations</samp> is used as well. Enabling this reduces precision of reciprocal square root results to about 16 bits for single precision and to 32 bits for double precision. </p> </dd> <dt>
 <span><code class="code">-mlow-precision-sqrt</code><a class="copiable-link" href="#index-mlow-precision-sqrt"> ¶</a></span>
</dt> <dt><code class="code">-mno-low-precision-sqrt</code></dt> <dd>
<p>Enable or disable the square root approximation. This option only has an effect if <samp class="option">-ffast-math</samp> or <samp class="option">-funsafe-math-optimizations</samp> is used as well. Enabling this reduces precision of square root results to about 16 bits for single precision and to 32 bits for double precision. If enabled, it implies <samp class="option">-mlow-precision-recip-sqrt</samp>. </p> </dd> <dt>
 <span><code class="code">-mlow-precision-div</code><a class="copiable-link" href="#index-mlow-precision-div"> ¶</a></span>
</dt> <dt><code class="code">-mno-low-precision-div</code></dt> <dd>
<p>Enable or disable the division approximation. This option only has an effect if <samp class="option">-ffast-math</samp> or <samp class="option">-funsafe-math-optimizations</samp> is used as well. Enabling this reduces precision of division results to about 16 bits for single precision and to 32 bits for double precision. </p> </dd> <dt><code class="code">-mtrack-speculation</code></dt> <dt><code class="code">-mno-track-speculation</code></dt> <dd>
<p>Enable or disable generation of additional code to track speculative execution through conditional branches. The tracking state can then be used by the compiler when expanding calls to <code class="code">__builtin_speculation_safe_copy</code> to permit a more efficient code sequence to be generated. </p> </dd> <dt><code class="code">-moutline-atomics</code></dt> <dt><code class="code">-mno-outline-atomics</code></dt> <dd>
<p>Enable or disable calls to out-of-line helpers to implement atomic operations. These helpers will, at runtime, determine if the LSE instructions from ARMv8.1-A can be used; if not, they will use the load/store-exclusive instructions that are present in the base ARMv8.0 ISA. </p> <p>This option is only applicable when compiling for the base ARMv8.0 instruction set. If using a later revision, e.g. <samp class="option">-march=armv8.1-a</samp> or <samp class="option">-march=armv8-a+lse</samp>, the ARMv8.1-Atomics instructions will be used directly. The same applies when using <samp class="option">-mcpu=</samp> when the selected cpu supports the ‘<samp class="samp">lse</samp>’ feature. This option is on by default. </p> </dd> <dt>
<span><code class="code">-march=<var class="var">name</var></code><a class="copiable-link" href="#index-march"> ¶</a></span>
</dt> <dd>
<p>Specify the name of the target architecture and, optionally, one or more feature modifiers. This option has the form <samp class="option">-march=<var class="var">arch</var><span class="r">{</span>+<span class="r">[</span>no<span class="r">]</span><var class="var">feature</var><span class="r">}*</span></samp>. </p> <p>The table below summarizes the permissible values for <var class="var">arch</var> and the features that they enable by default: </p> <table class="multitable"> <thead><tr>
<th width="20%">
<var class="var">arch</var> value</th>
<th width="20%">Architecture</th>
<th width="60%">Includes by default</th>
</tr></thead> <tbody>
<tr>
<td width="20%">‘<samp class="samp">armv8-a</samp>’</td>
<td width="20%">Armv8-A</td>
<td width="60%">‘<samp class="samp">+fp</samp>’, ‘<samp class="samp">+simd</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.1-a</samp>’</td>
<td width="20%">Armv8.1-A</td>
<td width="60%">‘<samp class="samp">armv8-a</samp>’, ‘<samp class="samp">+crc</samp>’, ‘<samp class="samp">+lse</samp>’, ‘<samp class="samp">+rdma</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.2-a</samp>’</td>
<td width="20%">Armv8.2-A</td>
<td width="60%">‘<samp class="samp">armv8.1-a</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.3-a</samp>’</td>
<td width="20%">Armv8.3-A</td>
<td width="60%">‘<samp class="samp">armv8.2-a</samp>’, ‘<samp class="samp">+pauth</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.4-a</samp>’</td>
<td width="20%">Armv8.4-A</td>
<td width="60%">‘<samp class="samp">armv8.3-a</samp>’, ‘<samp class="samp">+flagm</samp>’, ‘<samp class="samp">+fp16fml</samp>’, ‘<samp class="samp">+dotprod</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.5-a</samp>’</td>
<td width="20%">Armv8.5-A</td>
<td width="60%">‘<samp class="samp">armv8.4-a</samp>’, ‘<samp class="samp">+sb</samp>’, ‘<samp class="samp">+ssbs</samp>’, ‘<samp class="samp">+predres</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.6-a</samp>’</td>
<td width="20%">Armv8.6-A</td>
<td width="60%">‘<samp class="samp">armv8.5-a</samp>’, ‘<samp class="samp">+bf16</samp>’, ‘<samp class="samp">+i8mm</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.7-a</samp>’</td>
<td width="20%">Armv8.7-A</td>
<td width="60%">‘<samp class="samp">armv8.6-a</samp>’, ‘<samp class="samp">+ls64</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8.8-a</samp>’</td>
<td width="20%">Armv8.8-a</td>
<td width="60%">‘<samp class="samp">armv8.7-a</samp>’, ‘<samp class="samp">+mops</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv9-a</samp>’</td>
<td width="20%">Armv9-A</td>
<td width="60%">‘<samp class="samp">armv8.5-a</samp>’, ‘<samp class="samp">+sve</samp>’, ‘<samp class="samp">+sve2</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv9.1-a</samp>’</td>
<td width="20%">Armv9.1-A</td>
<td width="60%">‘<samp class="samp">armv9-a</samp>’, ‘<samp class="samp">+bf16</samp>’, ‘<samp class="samp">+i8mm</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv9.2-a</samp>’</td>
<td width="20%">Armv9.2-A</td>
<td width="60%">‘<samp class="samp">armv9.1-a</samp>’, ‘<samp class="samp">+ls64</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv9.3-a</samp>’</td>
<td width="20%">Armv9.3-A</td>
<td width="60%">‘<samp class="samp">armv9.2-a</samp>’, ‘<samp class="samp">+mops</samp>’</td>
</tr> <tr>
<td width="20%">‘<samp class="samp">armv8-r</samp>’</td>
<td width="20%">Armv8-R</td>
<td width="60%">‘<samp class="samp">armv8-r</samp>’</td>
</tr> </tbody> </table> <p>The value ‘<samp class="samp">native</samp>’ is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system. This option has no effect if the compiler is unable to recognize the architecture of the host system, </p> <p>The permissible values for <var class="var">feature</var> are listed in the sub-section on <a class="ref" href="#aarch64-feature-modifiers"><samp class="option">-march</samp> and <samp class="option">-mcpu</samp> Feature Modifiers</a>. Where conflicting feature modifiers are specified, the right-most feature is used. </p> <p>GCC uses <var class="var">name</var> to determine what kind of instructions it can emit when generating assembly code. If <samp class="option">-march</samp> is specified without either of <samp class="option">-mtune</samp> or <samp class="option">-mcpu</samp> also being specified, the code is tuned to perform well across a range of target processors implementing the target architecture. </p> </dd> <dt>
<span><code class="code">-mtune=<var class="var">name</var></code><a class="copiable-link" href="#index-mtune"> ¶</a></span>
</dt> <dd>
<p>Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: ‘<samp class="samp">generic</samp>’, ‘<samp class="samp">cortex-a35</samp>’, ‘<samp class="samp">cortex-a53</samp>’, ‘<samp class="samp">cortex-a55</samp>’, ‘<samp class="samp">cortex-a57</samp>’, ‘<samp class="samp">cortex-a72</samp>’, ‘<samp class="samp">cortex-a73</samp>’, ‘<samp class="samp">cortex-a75</samp>’, ‘<samp class="samp">cortex-a76</samp>’, ‘<samp class="samp">cortex-a76ae</samp>’, ‘<samp class="samp">cortex-a77</samp>’, ‘<samp class="samp">cortex-a65</samp>’, ‘<samp class="samp">cortex-a65ae</samp>’, ‘<samp class="samp">cortex-a34</samp>’, ‘<samp class="samp">cortex-a78</samp>’, ‘<samp class="samp">cortex-a78ae</samp>’, ‘<samp class="samp">cortex-a78c</samp>’, ‘<samp class="samp">ares</samp>’, ‘<samp class="samp">exynos-m1</samp>’, ‘<samp class="samp">emag</samp>’, ‘<samp class="samp">falkor</samp>’, ‘<samp class="samp">neoverse-512tvb</samp>’, ‘<samp class="samp">neoverse-e1</samp>’, ‘<samp class="samp">neoverse-n1</samp>’, ‘<samp class="samp">neoverse-n2</samp>’, ‘<samp class="samp">neoverse-v1</samp>’, ‘<samp class="samp">neoverse-v2</samp>’, ‘<samp class="samp">qdf24xx</samp>’, ‘<samp class="samp">saphira</samp>’, ‘<samp class="samp">phecda</samp>’, ‘<samp class="samp">xgene1</samp>’, ‘<samp class="samp">vulcan</samp>’, ‘<samp class="samp">octeontx</samp>’, ‘<samp class="samp">octeontx81</samp>’, ‘<samp class="samp">octeontx83</samp>’, ‘<samp class="samp">octeontx2</samp>’, ‘<samp class="samp">octeontx2t98</samp>’, ‘<samp class="samp">octeontx2t96</samp>’ ‘<samp class="samp">octeontx2t93</samp>’, ‘<samp class="samp">octeontx2f95</samp>’, ‘<samp class="samp">octeontx2f95n</samp>’, ‘<samp class="samp">octeontx2f95mm</samp>’, ‘<samp class="samp">a64fx</samp>’, ‘<samp class="samp">thunderx</samp>’, ‘<samp class="samp">thunderxt88</samp>’, ‘<samp class="samp">thunderxt88p1</samp>’, ‘<samp class="samp">thunderxt81</samp>’, ‘<samp class="samp">tsv110</samp>’, ‘<samp class="samp">thunderxt83</samp>’, ‘<samp class="samp">thunderx2t99</samp>’, ‘<samp class="samp">thunderx3t110</samp>’, ‘<samp class="samp">zeus</samp>’, ‘<samp class="samp">cortex-a57.cortex-a53</samp>’, ‘<samp class="samp">cortex-a72.cortex-a53</samp>’, ‘<samp class="samp">cortex-a73.cortex-a35</samp>’, ‘<samp class="samp">cortex-a73.cortex-a53</samp>’, ‘<samp class="samp">cortex-a75.cortex-a55</samp>’, ‘<samp class="samp">cortex-a76.cortex-a55</samp>’, ‘<samp class="samp">cortex-r82</samp>’, ‘<samp class="samp">cortex-x1</samp>’, ‘<samp class="samp">cortex-x1c</samp>’, ‘<samp class="samp">cortex-x2</samp>’, ‘<samp class="samp">cortex-x3</samp>’, ‘<samp class="samp">cortex-a510</samp>’, ‘<samp class="samp">cortex-a710</samp>’, ‘<samp class="samp">cortex-a715</samp>’, ‘<samp class="samp">ampere1</samp>’, ‘<samp class="samp">ampere1a</samp>’, and ‘<samp class="samp">native</samp>’. </p> <p>The values ‘<samp class="samp">cortex-a57.cortex-a53</samp>’, ‘<samp class="samp">cortex-a72.cortex-a53</samp>’, ‘<samp class="samp">cortex-a73.cortex-a35</samp>’, ‘<samp class="samp">cortex-a73.cortex-a53</samp>’, ‘<samp class="samp">cortex-a75.cortex-a55</samp>’, ‘<samp class="samp">cortex-a76.cortex-a55</samp>’ specify that GCC should tune for a big.LITTLE system. </p> <p>The value ‘<samp class="samp">neoverse-512tvb</samp>’ specifies that GCC should tune for Neoverse cores that (a) implement SVE and (b) have a total vector bandwidth of 512 bits per cycle. In other words, the option tells GCC to tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic instructions a cycle and that can execute an equivalent number of SVE arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE). This is more general than tuning for a specific core like Neoverse V1 but is more specific than the default tuning described below. </p> <p>Additionally on native AArch64 GNU/Linux systems the value ‘<samp class="samp">native</samp>’ tunes performance to the host system. This option has no effect if the compiler is unable to recognize the processor of the host system. </p> <p>Where none of <samp class="option">-mtune=</samp>, <samp class="option">-mcpu=</samp> or <samp class="option">-march=</samp> are specified, the code is tuned to perform well across a range of target processors. </p> <p>This option cannot be suffixed by feature modifiers. </p> </dd> <dt>
<span><code class="code">-mcpu=<var class="var">name</var></code><a class="copiable-link" href="#index-mcpu"> ¶</a></span>
</dt> <dd>
<p>Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form <samp class="option">-mcpu=<var class="var">cpu</var><span class="r">{</span>+<span class="r">[</span>no<span class="r">]</span><var class="var">feature</var><span class="r">}*</span></samp>, where the permissible values for <var class="var">cpu</var> are the same as those available for <samp class="option">-mtune</samp>. The permissible values for <var class="var">feature</var> are documented in the sub-section on <a class="ref" href="#aarch64-feature-modifiers"><samp class="option">-march</samp> and <samp class="option">-mcpu</samp> Feature Modifiers</a>. Where conflicting feature modifiers are specified, the right-most feature is used. </p> <p>GCC uses <var class="var">name</var> to determine what kind of instructions it can emit when generating assembly code (as if by <samp class="option">-march</samp>) and to determine the target processor for which to tune for performance (as if by <samp class="option">-mtune</samp>). Where this option is used in conjunction with <samp class="option">-march</samp> or <samp class="option">-mtune</samp>, those options take precedence over the appropriate part of this option. </p> <p><samp class="option">-mcpu=neoverse-512tvb</samp> is special in that it does not refer to a specific core, but instead refers to all Neoverse cores that (a) implement SVE and (b) have a total vector bandwidth of 512 bits a cycle. Unless overridden by <samp class="option">-march</samp>, <samp class="option">-mcpu=neoverse-512tvb</samp> generates code that can run on a Neoverse V1 core, since Neoverse V1 is the first Neoverse core with these properties. Unless overridden by <samp class="option">-mtune</samp>, <samp class="option">-mcpu=neoverse-512tvb</samp> tunes code in the same way as for <samp class="option">-mtune=neoverse-512tvb</samp>. </p> </dd> <dt>
<span><code class="code">-moverride=<var class="var">string</var></code><a class="copiable-link" href="#index-moverride"> ¶</a></span>
</dt> <dd>
<p>Override tuning decisions made by the back-end in response to a <samp class="option">-mtune=</samp> switch. The syntax, semantics, and accepted values for <var class="var">string</var> in this option are not guaranteed to be consistent across releases. </p> <p>This option is only intended to be useful when developing GCC. </p> </dd> <dt>
<span><code class="code">-mverbose-cost-dump</code><a class="copiable-link" href="#index-mverbose-cost-dump"> ¶</a></span>
</dt> <dd>
<p>Enable verbose cost model dumping in the debug dump files. This option is provided for use in debugging the compiler. </p> </dd> <dt>
 <span><code class="code">-mpc-relative-literal-loads</code><a class="copiable-link" href="#index-mpc-relative-literal-loads"> ¶</a></span>
</dt> <dt><code class="code">-mno-pc-relative-literal-loads</code></dt> <dd>
<p>Enable or disable PC-relative literal loads. With this option literal pools are accessed using a single instruction and emitted after each function. This limits the maximum size of functions to 1MB. This is enabled by default for <samp class="option">-mcmodel=tiny</samp>. </p> </dd> <dt>
<span><code class="code">-msign-return-address=<var class="var">scope</var></code><a class="copiable-link" href="#index-msign-return-address"> ¶</a></span>
</dt> <dd>
<p>Select the function scope on which return address signing will be applied. Permissible values are ‘<samp class="samp">none</samp>’, which disables return address signing, ‘<samp class="samp">non-leaf</samp>’, which enables pointer signing for functions which are not leaf functions, and ‘<samp class="samp">all</samp>’, which enables pointer signing for all functions. The default value is ‘<samp class="samp">none</samp>’. This option has been deprecated by -mbranch-protection. </p> </dd> <dt>
<span><code class="code">-mbranch-protection=<var class="var">none</var>|<var class="var">standard</var>|<var class="var">pac-ret</var>[+<var class="var">leaf</var>+<var class="var">b-key</var>]|<var class="var">bti</var></code><a class="copiable-link" href="#index-mbranch-protection"> ¶</a></span>
</dt> <dd>
<p>Select the branch protection features to use. ‘<samp class="samp">none</samp>’ is the default and turns off all types of branch protection. ‘<samp class="samp">standard</samp>’ turns on all types of branch protection features. If a feature has additional tuning options, then ‘<samp class="samp">standard</samp>’ sets it to its standard level. ‘<samp class="samp">pac-ret[+<var class="var">leaf</var>]</samp>’ turns on return address signing to its standard level: signing functions that save the return address to memory (non-leaf functions will practically always do this) using the a-key. The optional argument ‘<samp class="samp">leaf</samp>’ can be used to extend the signing to include leaf functions. The optional argument ‘<samp class="samp">b-key</samp>’ can be used to sign the functions with the B-key instead of the A-key. ‘<samp class="samp">bti</samp>’ turns on branch target identification mechanism. </p> </dd> <dt>
<span><code class="code">-mharden-sls=<var class="var">opts</var></code><a class="copiable-link" href="#index-mharden-sls"> ¶</a></span>
</dt> <dd>
<p>Enable compiler hardening against straight line speculation (SLS). <var class="var">opts</var> is a comma-separated list of the following options: </p>
<dl class="table"> <dt>‘<samp class="samp">retbr</samp>’</dt> <dt>‘<samp class="samp">blr</samp>’</dt> </dl> <p>In addition, ‘<samp class="samp">-mharden-sls=all</samp>’ enables all SLS hardening while ‘<samp class="samp">-mharden-sls=none</samp>’ disables all SLS hardening. </p> </dd> <dt>
<span><code class="code">-msve-vector-bits=<var class="var">bits</var></code><a class="copiable-link" href="#index-msve-vector-bits"> ¶</a></span>
</dt> <dd>
<p>Specify the number of bits in an SVE vector register. This option only has an effect when SVE is enabled. </p> <p>GCC supports two forms of SVE code generation: “vector-length agnostic” output that works with any size of vector register and “vector-length specific” output that allows GCC to make assumptions about the vector length when it is useful for optimization reasons. The possible values of ‘<samp class="samp">bits</samp>’ are: ‘<samp class="samp">scalable</samp>’, ‘<samp class="samp">128</samp>’, ‘<samp class="samp">256</samp>’, ‘<samp class="samp">512</samp>’, ‘<samp class="samp">1024</samp>’ and ‘<samp class="samp">2048</samp>’. Specifying ‘<samp class="samp">scalable</samp>’ selects vector-length agnostic output. At present ‘<samp class="samp">-msve-vector-bits=128</samp>’ also generates vector-length agnostic output for big-endian targets. All other values generate vector-length specific code. The behavior of these values may change in future releases and no value except ‘<samp class="samp">scalable</samp>’ should be relied on for producing code that is portable across different hardware SVE vector lengths. </p> <p>The default is ‘<samp class="samp">-msve-vector-bits=scalable</samp>’, which produces vector-length agnostic code. </p>
</dd> </dl> <ul class="mini-toc"> <li><a href="#g_t-march-and--mcpu-Feature-Modifiers" accesskey="1"><samp class="option">-march</samp> and <samp class="option">-mcpu</samp> Feature Modifiers</a></li> </ul> <div class="subsubsection-level-extent" id="g_t-march-and--mcpu-Feature-Modifiers"> <h1 class="subsubsection"><span>3.19.1.1 <samp class="option">-march</samp> and <samp class="option">-mcpu</samp> Feature Modifiers<a class="copiable-link" href="#g_t-march-and--mcpu-Feature-Modifiers"> ¶</a></span></h1>   <p>Feature modifiers used with <samp class="option">-march</samp> and <samp class="option">-mcpu</samp> can be any of the following and their inverses <samp class="option">no<var class="var">feature</var></samp>: </p> <dl class="table"> <dt>‘<samp class="samp">crc</samp>’</dt> <dd><p>Enable CRC extension. This is on by default for <samp class="option">-march=armv8.1-a</samp>. </p></dd> <dt>‘<samp class="samp">crypto</samp>’</dt> <dd><p>Enable Crypto extension. This also enables Advanced SIMD and floating-point instructions. </p></dd> <dt>‘<samp class="samp">fp</samp>’</dt> <dd><p>Enable floating-point instructions. This is on by default for all possible values for options <samp class="option">-march</samp> and <samp class="option">-mcpu</samp>. </p></dd> <dt>‘<samp class="samp">simd</samp>’</dt> <dd><p>Enable Advanced SIMD instructions. This also enables floating-point instructions. This is on by default for all possible values for options <samp class="option">-march</samp> and <samp class="option">-mcpu</samp>. </p></dd> <dt>‘<samp class="samp">sve</samp>’</dt> <dd><p>Enable Scalable Vector Extension instructions. This also enables Advanced SIMD and floating-point instructions. </p></dd> <dt>‘<samp class="samp">lse</samp>’</dt> <dd><p>Enable Large System Extension instructions. This is on by default for <samp class="option">-march=armv8.1-a</samp>. </p></dd> <dt>‘<samp class="samp">rdma</samp>’</dt> <dd><p>Enable Round Double Multiply Accumulate instructions. This is on by default for <samp class="option">-march=armv8.1-a</samp>. </p></dd> <dt>‘<samp class="samp">fp16</samp>’</dt> <dd><p>Enable FP16 extension. This also enables floating-point instructions. </p></dd> <dt>‘<samp class="samp">fp16fml</samp>’</dt> <dd>
<p>Enable FP16 fmla extension. This also enables FP16 extensions and floating-point instructions. This option is enabled by default for <samp class="option">-march=armv8.4-a</samp>. Use of this option with architectures prior to Armv8.2-A is not supported. </p> </dd> <dt>‘<samp class="samp">rcpc</samp>’</dt> <dd><p>Enable the RCpc extension. This enables the use of the LDAPR instructions for load-acquire atomic semantics, and passes it on to the assembler, enabling inline asm statements to use instructions from the RCpc extension. </p></dd> <dt>‘<samp class="samp">dotprod</samp>’</dt> <dd><p>Enable the Dot Product extension. This also enables Advanced SIMD instructions. </p></dd> <dt>‘<samp class="samp">aes</samp>’</dt> <dd><p>Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced SIMD instructions. </p></dd> <dt>‘<samp class="samp">sha2</samp>’</dt> <dd><p>Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions. </p></dd> <dt>‘<samp class="samp">sha3</samp>’</dt> <dd><p>Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMD instructions. Use of this option with architectures prior to Armv8.2-A is not supported. </p></dd> <dt>‘<samp class="samp">sm4</samp>’</dt> <dd><p>Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions. Use of this option with architectures prior to Armv8.2-A is not supported. </p></dd> <dt>‘<samp class="samp">profile</samp>’</dt> <dd><p>Enable the Statistical Profiling extension. This option is only to enable the extension at the assembler level and does not affect code generation. </p></dd> <dt>‘<samp class="samp">rng</samp>’</dt> <dd><p>Enable the Armv8.5-a Random Number instructions. This option is only to enable the extension at the assembler level and does not affect code generation. </p></dd> <dt>‘<samp class="samp">memtag</samp>’</dt> <dd><p>Enable the Armv8.5-a Memory Tagging Extensions. Use of this option with architectures prior to Armv8.5-A is not supported. </p></dd> <dt>‘<samp class="samp">sb</samp>’</dt> <dd><p>Enable the Armv8-a Speculation Barrier instruction. This option is only to enable the extension at the assembler level and does not affect code generation. This option is enabled by default for <samp class="option">-march=armv8.5-a</samp>. </p></dd> <dt>‘<samp class="samp">ssbs</samp>’</dt> <dd><p>Enable the Armv8-a Speculative Store Bypass Safe instruction. This option is only to enable the extension at the assembler level and does not affect code generation. This option is enabled by default for <samp class="option">-march=armv8.5-a</samp>. </p></dd> <dt>‘<samp class="samp">predres</samp>’</dt> <dd><p>Enable the Armv8-a Execution and Data Prediction Restriction instructions. This option is only to enable the extension at the assembler level and does not affect code generation. This option is enabled by default for <samp class="option">-march=armv8.5-a</samp>. </p></dd> <dt>‘<samp class="samp">sve2</samp>’</dt> <dd><p>Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE instructions. </p></dd> <dt>‘<samp class="samp">sve2-bitperm</samp>’</dt> <dd><p>Enable SVE2 bitperm instructions. This also enables SVE2 instructions. </p></dd> <dt>‘<samp class="samp">sve2-sm4</samp>’</dt> <dd><p>Enable SVE2 sm4 instructions. This also enables SVE2 instructions. </p></dd> <dt>‘<samp class="samp">sve2-aes</samp>’</dt> <dd><p>Enable SVE2 aes instructions. This also enables SVE2 instructions. </p></dd> <dt>‘<samp class="samp">sve2-sha3</samp>’</dt> <dd><p>Enable SVE2 sha3 instructions. This also enables SVE2 instructions. </p></dd> <dt>‘<samp class="samp">tme</samp>’</dt> <dd><p>Enable the Transactional Memory Extension. </p></dd> <dt>‘<samp class="samp">i8mm</samp>’</dt> <dd><p>Enable 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions. This option is enabled by default for <samp class="option">-march=armv8.6-a</samp>. Use of this option with architectures prior to Armv8.2-A is not supported. </p></dd> <dt>‘<samp class="samp">f32mm</samp>’</dt> <dd><p>Enable 32-bit Floating point Matrix Multiply instructions. This also enables SVE instructions. Use of this option with architectures prior to Armv8.2-A is not supported. </p></dd> <dt>‘<samp class="samp">f64mm</samp>’</dt> <dd><p>Enable 64-bit Floating point Matrix Multiply instructions. This also enables SVE instructions. Use of this option with architectures prior to Armv8.2-A is not supported. </p></dd> <dt>‘<samp class="samp">bf16</samp>’</dt> <dd><p>Enable brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions. This option is enabled by default for <samp class="option">-march=armv8.6-a</samp>. Use of this option with architectures prior to Armv8.2-A is not supported. </p></dd> <dt>‘<samp class="samp">ls64</samp>’</dt> <dd><p>Enable the 64-byte atomic load and store instructions for accelerators. This option is enabled by default for <samp class="option">-march=armv8.7-a</samp>. </p></dd> <dt>‘<samp class="samp">mops</samp>’</dt> <dd><p>Enable the instructions to accelerate memory operations like <code class="code">memcpy</code>, <code class="code">memmove</code>, <code class="code">memset</code>. This option is enabled by default for <samp class="option">-march=armv8.8-a</samp> </p></dd> <dt>‘<samp class="samp">flagm</samp>’</dt> <dd><p>Enable the Flag Manipulation instructions Extension. </p></dd> <dt>‘<samp class="samp">pauth</samp>’</dt> <dd><p>Enable the Pointer Authentication Extension. </p></dd> <dt>‘<samp class="samp">cssc</samp>’</dt> <dd>
<p>Enable the Common Short Sequence Compression instructions. </p> </dd> </dl> <p>Feature <samp class="option">crypto</samp> implies <samp class="option">aes</samp>, <samp class="option">sha2</samp>, and <samp class="option">simd</samp>, which implies <samp class="option">fp</samp>. Conversely, <samp class="option">nofp</samp> implies <samp class="option">nosimd</samp>, which implies <samp class="option">nocrypto</samp>, <samp class="option">noaes</samp> and <samp class="option">nosha2</samp>. </p> </div> </div>  <div class="nav-panel"> <p> Next: <a href="adapteva-epiphany-options">Adapteva Epiphany Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
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    &copy; Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
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