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<div class="subsection-level-extent" id="Blackfin-Options"> <div class="nav-panel"> <p> Next: <a href="c6x-options" accesskey="n" rel="next">C6X Options</a>, Previous: <a href="avr-options" accesskey="p" rel="prev">AVR Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div>  <h1 class="subsection" id="Blackfin-Options-1"><span>3.19.7 Blackfin Options<a class="copiable-link" href="#Blackfin-Options-1"> ¶</a></span></h1>  <dl class="table"> <dt>
<span><code class="code">-mcpu=<var class="var">cpu</var><span class="r">[</span>-<var class="var">sirevision</var><span class="r">]</span></code><a class="copiable-link" href="#index-mcpu_003d"> ¶</a></span>
</dt> <dd>
<p>Specifies the name of the target Blackfin processor. Currently, <var class="var">cpu</var> can be one of ‘<samp class="samp">bf512</samp>’, ‘<samp class="samp">bf514</samp>’, ‘<samp class="samp">bf516</samp>’, ‘<samp class="samp">bf518</samp>’, ‘<samp class="samp">bf522</samp>’, ‘<samp class="samp">bf523</samp>’, ‘<samp class="samp">bf524</samp>’, ‘<samp class="samp">bf525</samp>’, ‘<samp class="samp">bf526</samp>’, ‘<samp class="samp">bf527</samp>’, ‘<samp class="samp">bf531</samp>’, ‘<samp class="samp">bf532</samp>’, ‘<samp class="samp">bf533</samp>’, ‘<samp class="samp">bf534</samp>’, ‘<samp class="samp">bf536</samp>’, ‘<samp class="samp">bf537</samp>’, ‘<samp class="samp">bf538</samp>’, ‘<samp class="samp">bf539</samp>’, ‘<samp class="samp">bf542</samp>’, ‘<samp class="samp">bf544</samp>’, ‘<samp class="samp">bf547</samp>’, ‘<samp class="samp">bf548</samp>’, ‘<samp class="samp">bf549</samp>’, ‘<samp class="samp">bf542m</samp>’, ‘<samp class="samp">bf544m</samp>’, ‘<samp class="samp">bf547m</samp>’, ‘<samp class="samp">bf548m</samp>’, ‘<samp class="samp">bf549m</samp>’, ‘<samp class="samp">bf561</samp>’, ‘<samp class="samp">bf592</samp>’. </p> <p>The optional <var class="var">sirevision</var> specifies the silicon revision of the target Blackfin processor. Any workarounds available for the targeted silicon revision are enabled. If <var class="var">sirevision</var> is ‘<samp class="samp">none</samp>’, no workarounds are enabled. If <var class="var">sirevision</var> is ‘<samp class="samp">any</samp>’, all workarounds for the targeted processor are enabled. The <code class="code">__SILICON_REVISION__</code> macro is defined to two hexadecimal digits representing the major and minor numbers in the silicon revision. If <var class="var">sirevision</var> is ‘<samp class="samp">none</samp>’, the <code class="code">__SILICON_REVISION__</code> is not defined. If <var class="var">sirevision</var> is ‘<samp class="samp">any</samp>’, the <code class="code">__SILICON_REVISION__</code> is defined to be <code class="code">0xffff</code>. If this optional <var class="var">sirevision</var> is not used, GCC assumes the latest known silicon revision of the targeted Blackfin processor. </p> <p>GCC defines a preprocessor macro for the specified <var class="var">cpu</var>. For the ‘<samp class="samp">bfin-elf</samp>’ toolchain, this option causes the hardware BSP provided by libgloss to be linked in if <samp class="option">-msim</samp> is not given. </p> <p>Without this option, ‘<samp class="samp">bf532</samp>’ is used as the processor by default. </p> <p>Note that support for ‘<samp class="samp">bf561</samp>’ is incomplete. For ‘<samp class="samp">bf561</samp>’, only the preprocessor macro is defined. </p> </dd> <dt>
<span><code class="code">-msim</code><a class="copiable-link" href="#index-msim"> ¶</a></span>
</dt> <dd>
<p>Specifies that the program will be run on the simulator. This causes the simulator BSP provided by libgloss to be linked in. This option has effect only for ‘<samp class="samp">bfin-elf</samp>’ toolchain. Certain other options, such as <samp class="option">-mid-shared-library</samp> and <samp class="option">-mfdpic</samp>, imply <samp class="option">-msim</samp>. </p> </dd> <dt>
<span><code class="code">-momit-leaf-frame-pointer</code><a class="copiable-link" href="#index-momit-leaf-frame-pointer-1"> ¶</a></span>
</dt> <dd>
<p>Don’t keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set up and restore frame pointers and makes an extra register available in leaf functions. </p> </dd> <dt>
<span><code class="code">-mspecld-anomaly</code><a class="copiable-link" href="#index-mspecld-anomaly"> ¶</a></span>
</dt> <dd>
<p>When enabled, the compiler ensures that the generated code does not contain speculative loads after jump instructions. If this option is used, <code class="code">__WORKAROUND_SPECULATIVE_LOADS</code> is defined. </p> </dd> <dt>
 <span><code class="code">-mno-specld-anomaly</code><a class="copiable-link" href="#index-mno-specld-anomaly"> ¶</a></span>
</dt> <dd>
<p>Don’t generate extra code to prevent speculative loads from occurring. </p> </dd> <dt>
<span><code class="code">-mcsync-anomaly</code><a class="copiable-link" href="#index-mcsync-anomaly"> ¶</a></span>
</dt> <dd>
<p>When enabled, the compiler ensures that the generated code does not contain CSYNC or SSYNC instructions too soon after conditional branches. If this option is used, <code class="code">__WORKAROUND_SPECULATIVE_SYNCS</code> is defined. </p> </dd> <dt>
 <span><code class="code">-mno-csync-anomaly</code><a class="copiable-link" href="#index-mno-csync-anomaly"> ¶</a></span>
</dt> <dd>
<p>Don’t generate extra code to prevent CSYNC or SSYNC instructions from occurring too soon after a conditional branch. </p> </dd> <dt>
<span><code class="code">-mlow64k</code><a class="copiable-link" href="#index-mlow64k"> ¶</a></span>
</dt> <dd>
<p>When enabled, the compiler is free to take advantage of the knowledge that the entire program fits into the low 64k of memory. </p> </dd> <dt>
<span><code class="code">-mno-low64k</code><a class="copiable-link" href="#index-mno-low64k"> ¶</a></span>
</dt> <dd>
<p>Assume that the program is arbitrarily large. This is the default. </p> </dd> <dt>
<span><code class="code">-mstack-check-l1</code><a class="copiable-link" href="#index-mstack-check-l1"> ¶</a></span>
</dt> <dd>
<p>Do stack checking using information placed into L1 scratchpad memory by the uClinux kernel. </p> </dd> <dt>
<span><code class="code">-mid-shared-library</code><a class="copiable-link" href="#index-mid-shared-library"> ¶</a></span>
</dt> <dd>
<p>Generate code that supports shared libraries via the library ID method. This allows for execute in place and shared libraries in an environment without virtual memory management. This option implies <samp class="option">-fPIC</samp>. With a ‘<samp class="samp">bfin-elf</samp>’ target, this option implies <samp class="option">-msim</samp>. </p> </dd> <dt>
 <span><code class="code">-mno-id-shared-library</code><a class="copiable-link" href="#index-mno-id-shared-library"> ¶</a></span>
</dt> <dd>
<p>Generate code that doesn’t assume ID-based shared libraries are being used. This is the default. </p> </dd> <dt>
<span><code class="code">-mleaf-id-shared-library</code><a class="copiable-link" href="#index-mleaf-id-shared-library"> ¶</a></span>
</dt> <dd>
<p>Generate code that supports shared libraries via the library ID method, but assumes that this library or executable won’t link against any other ID shared libraries. That allows the compiler to use faster code for jumps and calls. </p> </dd> <dt>
 <span><code class="code">-mno-leaf-id-shared-library</code><a class="copiable-link" href="#index-mno-leaf-id-shared-library"> ¶</a></span>
</dt> <dd>
<p>Do not assume that the code being compiled won’t link against any ID shared libraries. Slower code is generated for jump and call insns. </p> </dd> <dt>
<span><code class="code">-mshared-library-id=n</code><a class="copiable-link" href="#index-mshared-library-id"> ¶</a></span>
</dt> <dd>
<p>Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library but is no more space- or time-efficient than omitting this option. </p> </dd> <dt>
<span><code class="code">-msep-data</code><a class="copiable-link" href="#index-msep-data"> ¶</a></span>
</dt> <dd>
<p>Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute in place in an environment without virtual memory management by eliminating relocations against the text section. </p> </dd> <dt>
 <span><code class="code">-mno-sep-data</code><a class="copiable-link" href="#index-mno-sep-data"> ¶</a></span>
</dt> <dd>
<p>Generate code that assumes that the data segment follows the text segment. This is the default. </p> </dd> <dt>
 <span><code class="code">-mlong-calls</code><a class="copiable-link" href="#index-mlong-calls-3"> ¶</a></span>
</dt> <dt><code class="code">-mno-long-calls</code></dt> <dd>
<p>Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 24-bit addressing range of the offset-based version of subroutine call instruction. </p> <p>This feature is not enabled by default. Specifying <samp class="option">-mno-long-calls</samp> restores the default behavior. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers. </p> </dd> <dt>
<span><code class="code">-mfast-fp</code><a class="copiable-link" href="#index-mfast-fp"> ¶</a></span>
</dt> <dd>
<p>Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard’s rules for checking inputs against Not-a-Number (NAN), in the interest of performance. </p> </dd> <dt>
<span><code class="code">-minline-plt</code><a class="copiable-link" href="#index-minline-plt"> ¶</a></span>
</dt> <dd>
<p>Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without <samp class="option">-mfdpic</samp>. </p> </dd> <dt>
<span><code class="code">-mmulticore</code><a class="copiable-link" href="#index-mmulticore"> ¶</a></span>
</dt> <dd>
<p>Build a standalone application for multicore Blackfin processors. This option causes proper start files and link scripts supporting multicore to be used, and defines the macro <code class="code">__BFIN_MULTICORE</code>. It can only be used with <samp class="option">-mcpu=bf561<span class="r">[</span>-<var class="var">sirevision</var><span class="r">]</span></samp>. </p> <p>This option can be used with <samp class="option">-mcorea</samp> or <samp class="option">-mcoreb</samp>, which selects the one-application-per-core programming model. Without <samp class="option">-mcorea</samp> or <samp class="option">-mcoreb</samp>, the single-application/dual-core programming model is used. In this model, the main function of Core B should be named as <code class="code">coreb_main</code>. </p> <p>If this option is not used, the single-core application programming model is used. </p> </dd> <dt>
<span><code class="code">-mcorea</code><a class="copiable-link" href="#index-mcorea"> ¶</a></span>
</dt> <dd>
<p>Build a standalone application for Core A of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core A, and the macro <code class="code">__BFIN_COREA</code> is defined. This option can only be used in conjunction with <samp class="option">-mmulticore</samp>. </p> </dd> <dt>
<span><code class="code">-mcoreb</code><a class="copiable-link" href="#index-mcoreb"> ¶</a></span>
</dt> <dd>
<p>Build a standalone application for Core B of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core B, and the macro <code class="code">__BFIN_COREB</code> is defined. When this option is used, <code class="code">coreb_main</code> should be used instead of <code class="code">main</code>. This option can only be used in conjunction with <samp class="option">-mmulticore</samp>. </p> </dd> <dt>
<span><code class="code">-msdram</code><a class="copiable-link" href="#index-msdram"> ¶</a></span>
</dt> <dd>
<p>Build a standalone application for SDRAM. Proper start files and link scripts are used to put the application into SDRAM, and the macro <code class="code">__BFIN_SDRAM</code> is defined. The loader should initialize SDRAM before loading the application. </p> </dd> <dt>
<span><code class="code">-micplb</code><a class="copiable-link" href="#index-micplb"> ¶</a></span>
</dt> <dd><p>Assume that ICPLBs are enabled at run time. This has an effect on certain anomaly workarounds. For Linux targets, the default is to assume ICPLBs are enabled; for standalone applications the default is off. </p></dd> </dl> </div>  <div class="nav-panel"> <p> Next: <a href="c6x-options">C6X Options</a>, Previous: <a href="avr-options">AVR Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
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    &copy; Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
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