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<div class="subsection-level-extent" id="IA-64-Options"> <div class="nav-panel"> <p> Next: <a href="lm32-options" accesskey="n" rel="next">LM32 Options</a>, Previous: <a href="hppa-options" accesskey="p" rel="prev">HPPA Options</a>, Up: <a href="submodel-options" accesskey="u" rel="up">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div> <h1 class="subsection" id="IA-64-Options-1"><span>3.19.20 IA-64 Options<a class="copiable-link" href="#IA-64-Options-1"> ¶</a></span></h1> <p>These are the ‘<samp class="samp">-m</samp>’ options defined for the Intel IA-64 architecture. </p> <dl class="table"> <dt>
<span><code class="code">-mbig-endian</code><a class="copiable-link" href="#index-mbig-endian-6"> ¶</a></span>
</dt> <dd>
<p>Generate code for a big-endian target. This is the default for HP-UX. </p> </dd> <dt>
<span><code class="code">-mlittle-endian</code><a class="copiable-link" href="#index-mlittle-endian-6"> ¶</a></span>
</dt> <dd>
<p>Generate code for a little-endian target. This is the default for AIX5 and GNU/Linux. </p> </dd> <dt>
<span><code class="code">-mgnu-as</code><a class="copiable-link" href="#index-mgnu-as"> ¶</a></span>
</dt> <dt><code class="code">-mno-gnu-as</code></dt> <dd>
<p>Generate (or don’t) code for the GNU assembler. This is the default. </p> </dd> <dt>
<span><code class="code">-mgnu-ld</code><a class="copiable-link" href="#index-mgnu-ld-1"> ¶</a></span>
</dt> <dt><code class="code">-mno-gnu-ld</code></dt> <dd>
<p>Generate (or don’t) code for the GNU linker. This is the default. </p> </dd> <dt>
<span><code class="code">-mno-pic</code><a class="copiable-link" href="#index-mno-pic"> ¶</a></span>
</dt> <dd>
<p>Generate code that does not use a global pointer register. The result is not position independent code, and violates the IA-64 ABI. </p> </dd> <dt>
<span><code class="code">-mvolatile-asm-stop</code><a class="copiable-link" href="#index-mvolatile-asm-stop"> ¶</a></span>
</dt> <dt><code class="code">-mno-volatile-asm-stop</code></dt> <dd>
<p>Generate (or don’t) a stop bit immediately before and after volatile asm statements. </p> </dd> <dt>
<span><code class="code">-mregister-names</code><a class="copiable-link" href="#index-mregister-names"> ¶</a></span>
</dt> <dt><code class="code">-mno-register-names</code></dt> <dd>
<p>Generate (or don’t) ‘<samp class="samp">in</samp>’, ‘<samp class="samp">loc</samp>’, and ‘<samp class="samp">out</samp>’ register names for the stacked registers. This may make assembler output more readable. </p> </dd> <dt>
<span><code class="code">-mno-sdata</code><a class="copiable-link" href="#index-mno-sdata-1"> ¶</a></span>
</dt> <dt><code class="code">-msdata</code></dt> <dd>
<p>Disable (or enable) optimizations that use the small data section. This may be useful for working around optimizer bugs. </p> </dd> <dt>
<span><code class="code">-mconstant-gp</code><a class="copiable-link" href="#index-mconstant-gp"> ¶</a></span>
</dt> <dd>
<p>Generate code that uses a single constant global pointer value. This is useful when compiling kernel code. </p> </dd> <dt>
<span><code class="code">-mauto-pic</code><a class="copiable-link" href="#index-mauto-pic"> ¶</a></span>
</dt> <dd>
<p>Generate code that is self-relocatable. This implies <samp class="option">-mconstant-gp</samp>. This is useful when compiling firmware code. </p> </dd> <dt>
<span><code class="code">-minline-float-divide-min-latency</code><a class="copiable-link" href="#index-minline-float-divide-min-latency"> ¶</a></span>
</dt> <dd>
<p>Generate code for inline divides of floating-point values using the minimum latency algorithm. </p> </dd> <dt>
<span><code class="code">-minline-float-divide-max-throughput</code><a class="copiable-link" href="#index-minline-float-divide-max-throughput"> ¶</a></span>
</dt> <dd>
<p>Generate code for inline divides of floating-point values using the maximum throughput algorithm. </p> </dd> <dt>
<span><code class="code">-mno-inline-float-divide</code><a class="copiable-link" href="#index-mno-inline-float-divide"> ¶</a></span>
</dt> <dd>
<p>Do not generate inline code for divides of floating-point values. </p> </dd> <dt>
<span><code class="code">-minline-int-divide-min-latency</code><a class="copiable-link" href="#index-minline-int-divide-min-latency"> ¶</a></span>
</dt> <dd>
<p>Generate code for inline divides of integer values using the minimum latency algorithm. </p> </dd> <dt>
<span><code class="code">-minline-int-divide-max-throughput</code><a class="copiable-link" href="#index-minline-int-divide-max-throughput"> ¶</a></span>
</dt> <dd>
<p>Generate code for inline divides of integer values using the maximum throughput algorithm. </p> </dd> <dt>
<span><code class="code">-mno-inline-int-divide</code><a class="copiable-link" href="#index-mno-inline-int-divide"> ¶</a></span>
</dt> <dd>
<p>Do not generate inline code for divides of integer values. </p> </dd> <dt>
<span><code class="code">-minline-sqrt-min-latency</code><a class="copiable-link" href="#index-minline-sqrt-min-latency"> ¶</a></span>
</dt> <dd>
<p>Generate code for inline square roots using the minimum latency algorithm. </p> </dd> <dt>
<span><code class="code">-minline-sqrt-max-throughput</code><a class="copiable-link" href="#index-minline-sqrt-max-throughput"> ¶</a></span>
</dt> <dd>
<p>Generate code for inline square roots using the maximum throughput algorithm. </p> </dd> <dt>
<span><code class="code">-mno-inline-sqrt</code><a class="copiable-link" href="#index-mno-inline-sqrt"> ¶</a></span>
</dt> <dd>
<p>Do not generate inline code for <code class="code">sqrt</code>. </p> </dd> <dt>
<span><code class="code">-mfused-madd</code><a class="copiable-link" href="#index-mfused-madd"> ¶</a></span>
</dt> <dt><code class="code">-mno-fused-madd</code></dt> <dd>
<p>Do (don’t) generate code that uses the fused multiply/add or multiply/subtract instructions. The default is to use these instructions. </p> </dd> <dt>
<span><code class="code">-mno-dwarf2-asm</code><a class="copiable-link" href="#index-mno-dwarf2-asm"> ¶</a></span>
</dt> <dt><code class="code">-mdwarf2-asm</code></dt> <dd>
<p>Don’t (or do) generate assembler code for the DWARF line number debugging info. This may be useful when not using the GNU assembler. </p> </dd> <dt>
<span><code class="code">-mearly-stop-bits</code><a class="copiable-link" href="#index-mearly-stop-bits"> ¶</a></span>
</dt> <dt><code class="code">-mno-early-stop-bits</code></dt> <dd>
<p>Allow stop bits to be placed earlier than immediately preceding the instruction that triggered the stop bit. This can improve instruction scheduling, but does not always do so. </p> </dd> <dt>
<span><code class="code">-mfixed-range=<var class="var">register-range</var></code><a class="copiable-link" href="#index-mfixed-range-1"> ¶</a></span>
</dt> <dd>
<p>Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma. </p> </dd> <dt>
<span><code class="code">-mtls-size=<var class="var">tls-size</var></code><a class="copiable-link" href="#index-mtls-size-1"> ¶</a></span>
</dt> <dd>
<p>Specify bit size of immediate TLS offsets. Valid values are 14, 22, and 64. </p> </dd> <dt>
<span><code class="code">-mtune=<var class="var">cpu-type</var></code><a class="copiable-link" href="#index-mtune-7"> ¶</a></span>
</dt> <dd>
<p>Tune the instruction scheduling for a particular CPU, Valid values are ‘<samp class="samp">itanium</samp>’, ‘<samp class="samp">itanium1</samp>’, ‘<samp class="samp">merced</samp>’, ‘<samp class="samp">itanium2</samp>’, and ‘<samp class="samp">mckinley</samp>’. </p> </dd> <dt>
<span><code class="code">-milp32</code><a class="copiable-link" href="#index-milp32"> ¶</a></span>
</dt> <dt><code class="code">-mlp64</code></dt> <dd>
<p>Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. These are HP-UX specific flags. </p> </dd> <dt>
<span><code class="code">-mno-sched-br-data-spec</code><a class="copiable-link" href="#index-mno-sched-br-data-spec"> ¶</a></span>
</dt> <dt><code class="code">-msched-br-data-spec</code></dt> <dd>
<p>(Dis/En)able data speculative scheduling before reload. This results in generation of <code class="code">ld.a</code> instructions and the corresponding check instructions (<code class="code">ld.c</code> / <code class="code">chk.a</code>). The default setting is disabled. </p> </dd> <dt>
<span><code class="code">-msched-ar-data-spec</code><a class="copiable-link" href="#index-msched-ar-data-spec"> ¶</a></span>
</dt> <dt><code class="code">-mno-sched-ar-data-spec</code></dt> <dd>
<p>(En/Dis)able data speculative scheduling after reload. This results in generation of <code class="code">ld.a</code> instructions and the corresponding check instructions (<code class="code">ld.c</code> / <code class="code">chk.a</code>). The default setting is enabled. </p> </dd> <dt>
<span><code class="code">-mno-sched-control-spec</code><a class="copiable-link" href="#index-mno-sched-control-spec"> ¶</a></span>
</dt> <dt><code class="code">-msched-control-spec</code></dt> <dd>
<p>(Dis/En)able control speculative scheduling. This feature is available only during region scheduling (i.e. before reload). This results in generation of the <code class="code">ld.s</code> instructions and the corresponding check instructions <code class="code">chk.s</code>. The default setting is disabled. </p> </dd> <dt>
<span><code class="code">-msched-br-in-data-spec</code><a class="copiable-link" href="#index-msched-br-in-data-spec"> ¶</a></span>
</dt> <dt><code class="code">-mno-sched-br-in-data-spec</code></dt> <dd>
<p>(En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads before reload. This is effective only with <samp class="option">-msched-br-data-spec</samp> enabled. The default setting is enabled. </p> </dd> <dt>
<span><code class="code">-msched-ar-in-data-spec</code><a class="copiable-link" href="#index-msched-ar-in-data-spec"> ¶</a></span>
</dt> <dt><code class="code">-mno-sched-ar-in-data-spec</code></dt> <dd>
<p>(En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads after reload. This is effective only with <samp class="option">-msched-ar-data-spec</samp> enabled. The default setting is enabled. </p> </dd> <dt>
<span><code class="code">-msched-in-control-spec</code><a class="copiable-link" href="#index-msched-in-control-spec"> ¶</a></span>
</dt> <dt><code class="code">-mno-sched-in-control-spec</code></dt> <dd>
<p>(En/Dis)able speculative scheduling of the instructions that are dependent on the control speculative loads. This is effective only with <samp class="option">-msched-control-spec</samp> enabled. The default setting is enabled. </p> </dd> <dt>
<span><code class="code">-mno-sched-prefer-non-data-spec-insns</code><a class="copiable-link" href="#index-mno-sched-prefer-non-data-spec-insns"> ¶</a></span>
</dt> <dt><code class="code">-msched-prefer-non-data-spec-insns</code></dt> <dd>
<p>If enabled, data-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the data speculation much more conservative. The default setting is disabled. </p> </dd> <dt>
<span><code class="code">-mno-sched-prefer-non-control-spec-insns</code><a class="copiable-link" href="#index-mno-sched-prefer-non-control-spec-insns"> ¶</a></span>
</dt> <dt><code class="code">-msched-prefer-non-control-spec-insns</code></dt> <dd>
<p>If enabled, control-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the control speculation much more conservative. The default setting is disabled. </p> </dd> <dt>
<span><code class="code">-mno-sched-count-spec-in-critical-path</code><a class="copiable-link" href="#index-mno-sched-count-spec-in-critical-path"> ¶</a></span>
</dt> <dt><code class="code">-msched-count-spec-in-critical-path</code></dt> <dd>
<p>If enabled, speculative dependencies are considered during computation of the instructions priorities. This makes the use of the speculation a bit more conservative. The default setting is disabled. </p> </dd> <dt>
<span><code class="code">-msched-spec-ldc</code><a class="copiable-link" href="#index-msched-spec-ldc"> ¶</a></span>
</dt> <dd>
<p>Use a simple data speculation check. This option is on by default. </p> </dd> <dt>
<span><code class="code">-msched-control-spec-ldc</code><a class="copiable-link" href="#index-msched-spec-ldc-1"> ¶</a></span>
</dt> <dd>
<p>Use a simple check for control speculation. This option is on by default. </p> </dd> <dt>
<span><code class="code">-msched-stop-bits-after-every-cycle</code><a class="copiable-link" href="#index-msched-stop-bits-after-every-cycle"> ¶</a></span>
</dt> <dd>
<p>Place a stop bit after every cycle when scheduling. This option is on by default. </p> </dd> <dt>
<span><code class="code">-msched-fp-mem-deps-zero-cost</code><a class="copiable-link" href="#index-msched-fp-mem-deps-zero-cost"> ¶</a></span>
</dt> <dd>
<p>Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same instruction group. This option is disabled by default. </p> </dd> <dt>
<span><code class="code">-msel-sched-dont-check-control-spec</code><a class="copiable-link" href="#index-msel-sched-dont-check-control-spec"> ¶</a></span>
</dt> <dd>
<p>Generate checks for control speculation in selective scheduling. This flag is disabled by default. </p> </dd> <dt>
<span><code class="code">-msched-max-memory-insns=<var class="var">max-insns</var></code><a class="copiable-link" href="#index-msched-max-memory-insns"> ¶</a></span>
</dt> <dd>
<p>Limit on the number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same instruction group. Frequently useful to prevent cache bank conflicts. The default value is 1. </p> </dd> <dt>
<span><code class="code">-msched-max-memory-insns-hard-limit</code><a class="copiable-link" href="#index-msched-max-memory-insns-hard-limit"> ¶</a></span>
</dt> <dd>
<p>Makes the limit specified by <samp class="option">msched-max-memory-insns</samp> a hard limit, disallowing more than that number in an instruction group. Otherwise, the limit is “soft”, meaning that non-memory operations are preferred when the limit is reached, but memory operations may still be scheduled. </p> </dd> </dl> </div> <div class="nav-panel"> <p> Next: <a href="lm32-options">LM32 Options</a>, Previous: <a href="hppa-options">HPPA Options</a>, Up: <a href="submodel-options">Machine-Dependent Options</a> [<a href="index#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="indices" title="Index" rel="index">Index</a>]</p> </div><div class="_attribution">
<p class="_attribution-p">
© Free Software Foundation<br>Licensed under the GNU Free Documentation License, Version 1.3.<br>
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